Optimal Layout Synthesis for Quantum Circuits as Classical Planning (full version)
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Abstract (arXiv)
In Layout Synthesis, the logical qubits of a quantum circuit are mapped to the physical qubits of a given quantum hardware platform, taking into account the connectivity of physical qubits. This involves inserting SWAP gates before an operation is applied on distant qubits. Optimal Layout Synthesis is crucial for practical Quantum Computing on current error-prone hardware: Minimizing the number of SWAP gates directly mitigates the error rates when running quantum circuits. In recent years, several approaches have been proposed for minimizing the required SWAP insertions. The proposed exact approaches can only scale to a small number of qubits. Proving that a number of swap insertions is optimal is much harder than producing near optimal mappings. In this paper, we provide two encodings for Optimal Layout Synthesis as a classical planning problem. We use optimal classical planners to synthesize the optimal layout for a standard set of benchmarks. Our results show the scalability of our approach compared to previous leading approaches. We can optimally map circuits with 9 qubits onto a 14 qubit platform, which could not be handled before by exact methods.
Key facts. Cited by 7 papers in the map (data through 7 Oct 2026). Builds on 7 of its 40 references that are in the map. First posted on arXiv 24 Apr 2023.
Builds on
7 of 40 references.
References · 7
- 2022Qubit Mapping and Routing via MaxSATcited by 8
- 2020Optimality Study of Existing Quantum Computing Layout Synthesis Toolscited by 7
- 2020Optimal Layout Synthesis for Quantum Computingcited by 6
- 2018Comparing and Integrating Constraint Programming and Temporal Planning for Quantum Circuit Compilationcited by 5
- 2020A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Eracited by 5
- 2021Classical Planning as QBF without Grounding (extended version)cited by 5
- 2020Planning for Compilation of a Quantum Algorithm for Graph Coloringcited by 1
Built on by
Citing papers per year: 2024: 3; 2025: 3; 2026: 1.
7 papers.
- 2024Learning to rank quantum circuits for hardware-optimized performance enhancementcited by 4
- 2024Optimal Layout-Aware CNOT Circuit Synthesis with Qubit Permutationcited by 4
- 2024Optimal Layout Synthesis for Deep Quantum Circuits on NISQ Processors with 100+ Qubitscited by 3
- 2025CNOT-Optimal Clifford Synthesis as SATcited by 3
- 2025Depth-Optimal Quantum Layout Synthesis as SATcited by 0
- 2025Two Constraint Compilation Methods for Lifted Planningcited by 0
- 2026A 12-CNOT Double Qubit Excitation Gatecited by 0
- 2026A 12-CNOT Double Qubit Excitation Gate12 Aug 2026
- 2025Two Constraint Compilation Methods for Lifted Planning13 Nov 2025
- 2025Depth-Optimal Quantum Layout Synthesis as SAT7 Jun 2025
- 2025CNOT-Optimal Clifford Synthesis as SAT1 Apr 2025
- 2024Optimal Layout-Aware CNOT Circuit Synthesis with Qubit Permutation8 Aug 2024
- 2024Learning to rank quantum circuits for hardware-optimized performance enhancement9 Apr 2024
- 2024Optimal Layout Synthesis for Deep Quantum Circuits on NISQ Processors with 100+ Qubits18 Mar 2024