mlsanityData to 7 Oct 2026

Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits

arXiv 2302.14576 ↗First posted 28 Feb 2023cs.LG cs.ARcited by 11

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Abstract (arXiv)

Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications for domains that feature ultra-low cost, conformity, and non-toxicity requirements that silicon-based systems cannot deliver. Nevertheless, large feature sizes in PE prohibit the realization of complex printed ML circuits. In this work, we present, for the first time, an automated printed-aware software/hardware co-design framework that exploits approximate computing principles to enable ultra-resource constrained printed multilayer perceptrons (MLPs). Our evaluation demonstrates that, compared to the state-of-the-art baseline, our circuits feature on average 6x (5.7x) lower area (power) and less than 1% accuracy loss.

Key facts. Cited by 11 papers in the map (data through 7 Oct 2026). Builds on 4 of its 32 references that are in the map. First posted on arXiv 28 Feb 2023.

Builds on

4 of 32 references.

References · 4

  1. 2019ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retrainingcited by 28
  2. 2022Cross-Layer Approximation For Printed Machine Learning Circuitscited by 12
  3. 2021Control Variate Approximation for DNN Acceleratorscited by 11
  4. 2022CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAscited by 11

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Cited by year

Citing papers per year: 2023: 3; 2024: 1; 2025: 7.

11 papers.