Revet: A Language and Compiler for Dataflow Threads
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Abstract (arXiv)
Spatial dataflow architectures such as reconfigurable dataflow accelerators (RDA) can provide much higher performance and efficiency than CPUs and GPUs. In particular, vectorized reconfigurable dataflow accelerators (vRDA) in recent literature represent a design point that enhances the efficiency of dataflow architectures with vectorization. Today, vRDAs can be exploited using either hardcoded kernels or MapReduce languages like Spatial, which cannot vectorize data-dependent control flow. In contrast, CPUs and GPUs can be programmed using general-purpose threaded abstractions. The ideal combination would be the generality of a threaded programming model coupled with the efficient execution model of a vRDA. We introduce Revet: a programming model, compiler, and execution model that lets threaded applications run efficiently on vRDAs. The Revet programming language uses threads to support a broader range of applications than Spatial's parallel patterns, and our MLIR-based compiler lowers this language to a generic dataflow backend that operates on streaming tensors. Finally, we show that mapping threads to dataflow outperforms GPUs, the current state-of-the-art for threaded accelerators, by 3.8x.
Key facts. Cited by 6 papers in the map (data through 7 Oct 2026). First posted on arXiv 13 Feb 2023.
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Citing papers per year: 2023: 1; 2024: 1; 2025: 4.
6 papers.
- 2025Adaptive Self-improvement LLM Agentic System for ML Library Developmentcited by 16
- 2024Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T10cited by 5
- 2025Dato: A Task-Based Programming Model for Dataflow Acceleratorscited by 5
- 2023A Dataflow Compiler for Efficient LLM Inference using Custom Microscaling Formatscited by 2
- 2025From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIRcited by 2
- 2025Streaming Tensor Programs: A Streaming Abstraction for Dynamic Parallelismcited by 0
- 2025Streaming Tensor Programs: A Streaming Abstraction for Dynamic Parallelism11 Nov 2025
- 2025From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR16 Oct 2025
- 2025Dato: A Task-Based Programming Model for Dataflow Accelerators8 Sep 2025
- 2025Adaptive Self-improvement LLM Agentic System for ML Library Development4 Feb 2025
- 2024Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T109 Aug 2024
- 2023A Dataflow Compiler for Efficient LLM Inference using Custom Microscaling Formats28 Jul 2023