mlsanityData to 7 Oct 2026

FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training

arXiv 2212.03515 ↗First posted 7 Dec 2022eess.SP cs.IT cs.LGcited by 2

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Abstract (arXiv)

We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.

Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 6 of its 21 references that are in the map. First posted on arXiv 7 Dec 2022.

Builds on

6 of 21 references.

References · 6

  1. 2020From Learning to Meta-Learning: Reduced Training Overhead and Complexity for Communication Systemscited by 18
  2. 2017Nonlinear Interference Mitigation via Deep Neural Networkscited by 13
  3. 2020Physics-Based Deep Learning for Fiber-Optic Communication Systemscited by 9
  4. 2020Model-Based Machine Learning for Joint Digital Backpropagation and PMD Compensationcited by 5
  5. 2022Towards FPGA Implementation of Neural Network-Based Nonlinearity Mitigation Equalizers in Coherent Optical Transmission Systemscited by 4
  6. 2018ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filterscited by 1

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 1; 2024: 0; 2025: 0; 2026: 1.

2 papers.

  1. 2023Unsupervised ANN-Based Equalizer and Its Trainable FPGA Implementationcited by 2
  2. 2026Ultrafast On-Chip Online Learning via Spline Locality in Kolmogorov-Arnold Networkscited by 0