Automated Circuit Sizing with Multi-objective Optimization based on Differential Evolution and Bayesian Inference
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Abstract (arXiv)
With the ever increasing complexity of specifications, manual sizing for analog circuits recently became very challenging. Especially for innovative, large-scale circuits designs, with tens of design variables, operating conditions and conflicting objectives to be optimized, design engineers spend many weeks, running time-consuming simulations, in their attempt at finding the right configuration. Recent years brought machine learning and optimization techniques to the field of analog circuits design, with evolutionary algorithms and Bayesian models showing good results for circuit sizing. In this context, we introduce a design optimization method based on Generalized Differential Evolution 3 (GDE3) and Gaussian Processes (GPs). The proposed method is able to perform sizing for complex circuits with a large number of design variables and many conflicting objectives to be optimized. While state-of-the-art methods reduce multi-objective problems to single-objective optimization and potentially induce a prior bias, we search directly over the multi-objective space using Pareto dominance and ensure that diverse solutions are provided to the designers to choose from. To the best of our knowledge, the proposed method is the first to specifically address the diversity of the solutions, while also focusing on minimizing the number of simulations required to reach feasible configurations. We evaluate the introduced method on two voltage regulators showing different levels of complexity and we highlight that the proposed innovative candidate selection method and survival policy leads to obtaining feasible solutions, with a high degree of diversity, much faster than with GDE3 or Bayesian Optimization-based algorithms.
Key facts. Cited by 3 papers in the map (data through 7 Oct 2026). Builds on 5 of its 51 references that are in the map. First posted on arXiv 6 Jun 2022.
Builds on
5 of 51 references.
References · 5
- 2020GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learningcited by 89
- 2018Learning to Design Circuitscited by 17
- 2017Two-Archive Evolutionary Algorithm for Constrained Multi-Objective Optimizationcited by 13
- 2019Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Networkcited by 8
- 2019Multi-objective multi-generation Gaussian process optimizer for design optimizationcited by 2
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Citing papers per year: 2025: 1; 2026: 2.
3 papers.
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimizationcited by 5
- 2026ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Explorationcited by 1
- 2026Deterministic Pareto-Optimal Policy Synthesis for Multi-Objective Reinforcement Learningcited by 0
- 2026ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration5 Aug 2026
- 2026Deterministic Pareto-Optimal Policy Synthesis for Multi-Objective Reinforcement Learning24 Jun 2026
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization24 Nov 2025