COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks
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Abstract (arXiv)
Graph convolutional networks (GCNs) have shown remarkable learning capabilities when processing graph-structured data found inherently in many application areas. GCNs distribute the outputs of neural networks embedded in each vertex over multiple iterations to take advantage of the relations captured by the underlying graphs. Consequently, they incur a significant amount of computation and irregular communication overheads, which call for GCN-specific hardware accelerators. To this end, this paper presents a communication-aware in-memory computing architecture (COIN) for GCN hardware acceleration. Besides accelerating the computation using custom compute elements (CE) and in-memory computing, COIN aims at minimizing the intra- and inter-CE communication in GCN operations to optimize the performance and energy efficiency. Experimental evaluations with widely used datasets show up to 105x improvement in energy consumption compared to state-of-the-art GCN accelerator.
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References · 19
- 2016Semi-Supervised Classification with Graph Convolutional Networkscited by 11,282
- 2017Inductive Representation Learning on Large Graphscited by 6,284
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- 2015Convolutional Networks on Graphs for Learning Molecular Fingerprintscited by 751
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- 2019Deep Graph Library: A Graph-Centric, Highly-Performant Package for Graph Neural Networkscited by 241
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- 2019PyTorch-BigGraph: A Large-scale Graph Embedding Systemcited by 118
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- 2019EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networkscited by 42
- 2020GRIP: A Graph Neural Network Accelerator Architecturecited by 37
7 more
- 2021DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Eracited by 27
- 2017GraphR: Accelerating Graph Processing Using ReRAMcited by 19
- 2020Rubik: A Hierarchical Architecture for Efficient Graph Learningcited by 7
- 2021SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networkscited by 6
- 2021ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networkscited by 5
- 2021Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networkscited by 3
- 2015A Framework for General Sparse Matrix-Matrix Multiplication on GPUs and Heterogeneous Processorscited by 2
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