Detecting silent data corruptions in the wild
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Abstract (arXiv)
Silent Errors within hardware devices occur when an internal defect manifests in a part of the circuit which does not have check logic to detect the incorrect circuit operation. The results of such a defect can range from flipping a single bit in a single data value, up to causing the software to execute the wrong instructions. Silent data corruptions (SDC) in hardware impact computational integrity for large-scale applications. Manifestations of silent errors are accelerated by datapath variations, temperature variance, and age, among other silicon factors. These errors do not leave any record or trace in system logs. As a result, silent errors stay undetected within workloads, and their effects can propagate across several services, causing problems to appear in systems far removed from the original defect. In this paper, we describe testing strategies to detect silent data corruptions within a large scale infrastructure. Given the challenging nature of the problem, we experimented with different methods for detection and mitigation. We compare and contrast two such approaches - 1. Fleetscanner (out-of-production testing) and 2. Ripple (in-production testing).We evaluate the infrastructure tradeoffs associated with the silicon testing funnel across 3+ years of production experience.
Key facts. Cited by 7 papers in the map (data through 14 Oct 2026). First posted on arXiv 16 Mar 2022.
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Citing papers per year: 2022: 1; 2023: 1; 2024: 2; 2025: 2; 2026: 1.
7 papers.
- 2024ATTNChecker: Highly-Optimized Fault Tolerant Attention for Large Language Model Trainingcited by 12
- 2026Exploring Silent Data Corruption as a Reliability Challenge in LLM Trainingcited by 3
- 2022PyGFI: Analyzing and Enhancing Robustness of Graph Neural Networks Against Hardware Errorscited by 2
- 2024PVF:Understanding AI Vulnerability Against SDCscited by 2
- 2023Evaluating and Enhancing Robustness of Deep Recommendation Systems Against Hardware Errorscited by 1
- 2025Ralts: Robust Aggregation for Enhancing Graph Neural Network Resilience on Bit-flip Errorscited by 0
- 2025A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faultscited by 0
- 2026Exploring Silent Data Corruption as a Reliability Challenge in LLM Training1 Apr 2026
- 2025A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults8 Sep 2025
- 2025Ralts: Robust Aggregation for Enhancing Graph Neural Network Resilience on Bit-flip Errors24 Jul 2025
- 2024ATTNChecker: Highly-Optimized Fault Tolerant Attention for Large Language Model Training15 Oct 2024
- 2024PVF:Understanding AI Vulnerability Against SDCs2 May 2024
- 2023Evaluating and Enhancing Robustness of Deep Recommendation Systems Against Hardware Errors17 Jul 2023
- 2022PyGFI: Analyzing and Enhancing Robustness of Graph Neural Networks Against Hardware Errors7 Dec 2022