Learning from distinctive candidates to optimize reduced-precision convolution program on tensor cores
Not on the map. Why?
Abstract (arXiv)
Convolution is one of the fundamental operations of deep neural networks with demanding matrix computation. In a graphic processing unit (GPU), Tensor Core is a specialized matrix processing hardware equipped with reduced-precision matrix-multiply-accumulate (MMA) instructions to increase throughput. However, it is challenging to achieve optimal performance since the best scheduling of MMA instructions varies for different convolution sizes. In particular, reduced-precision MMA requires many elements grouped as a matrix operand, seriously limiting data reuse and imposing packing and layout overhead on the schedule. This work proposes an automatic scheduling method of reduced-precision MMA for convolution operation. In this method, we devise a search space that explores the thread tile and warp sizes to increase the data reuse despite a large matrix operand of reduced-precision MMA. The search space also includes options of register-level packing and layout optimization to lesson overhead of handling reduced-precision data. Finally, we propose a search algorithm to find the best schedule by learning from the distinctive candidates. This reduced-precision MMA optimization method is evaluated on convolution operations of popular neural networks to demonstrate substantial speedup on Tensor Core compared to the state of the arts with shortened search time.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 11 of its 21 references that are in the map. First posted on arXiv 11 Feb 2022.
Builds on
11 of 21 references.
References · 11
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2020An Image is Worth 16x16 Words: Transformers for Image Recognition at Scalecited by 29,915
- 2015Rethinking the Inception Architecture for Computer Visioncited by 5,451
- 2018PACT: Parameterized Clipping Activation for Quantized Neural Networkscited by 456
- 2020Ansor: Generating High-Performance Tensor Programs for Deep Learningcited by 199
- 2018Learning to Optimize Tensor Programscited by 138
- 2021APNN-TC: Accelerating Arbitrary Precision Neural Networks on Ampere GPU Tensor Corescited by 12
- 2020Accelerating Sparse Matrix-Matrix Multiplication with GPU Tensor Corescited by 9
- 2020Automatic Kernel Generation for Volta Tensor Corescited by 8
- 2020GPU Tensor Cores for fast Arithmetic Reductionscited by 4
- 2019Analyzing GPU Tensor Core Potential for Fast Reductionscited by 1
Built on by
Citing papers per year: 2026: 1.
1 paper.
- 2026Hardware-Aware Features for CUTLASS Kernel Selectioncited by 0
- 2026Hardware-Aware Features for CUTLASS Kernel Selection28 Sep 2026