Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA
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Abstract (arXiv)
Tensor decomposition has become an essential tool in many applications in various domains, including machine learning. Sparse Matricized Tensor Times Khatri-Rao Product (MTTKRP) is one of the most computationally expensive kernels in tensor computations. Despite having significant computational parallelism, MTTKRP is a challenging kernel to optimize due to its irregular memory access characteristics. This paper focuses on a multi-faceted memory system, which explores the spatial and temporal locality of the data structures of MTTKRP. Further, users can reconfigure our design depending on the behavior of the compute units used in the FPGA accelerator. Our system efficiently accesses all the MTTKRP data structures while reducing the total memory access time, using a distributed cache and Direct Memory Access (DMA) subsystem. Moreover, our work improves the memory access time by 3.5x compared with commercial memory controller IPs. Also, our system shows 2x and 1.26x speedups compared with cache-only and DMA-only memory systems, respectively.
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 7 of its 29 references that are in the map. First posted on arXiv 18 Sep 2021.
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References · 7
- 2016Tensor Decomposition for Signal Processing and Machine Learningcited by 223
- 2018Generalized Canonical Polyadic Tensor Decompositioncited by 34
- 2019Stochastic Gradients for Large-Scale Tensor Decompositioncited by 16
- 2018On the Connection Between Learning Two-Layers Neural Networks and Tensor Decompositioncited by 14
- 2019Load-Balanced Sparse MTTKRP on GPUscited by 5
- 2021A High Throughput Parallel Hash Table on FPGA using XOR-based Memorycited by 1
- 2021Programmable FPGA-based Memory Controllercited by 1
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