GPTPU: Accelerating Applications using Edge Tensor Processing Units
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Abstract (arXiv)
Neural network (NN) accelerators have been integrated into a wide-spectrum of computer systems to accommodate the rapidly growing demands for artificial intelligence (AI) and machine learning (ML) applications. NN accelerators share the idea of providing native hardware support for operations on multidimensional tensor data. Therefore, NN accelerators are theoretically tensor processors that can improve system performance for any problem that uses tensors as inputs/outputs. Unfortunately, commercially available NN accelerators only expose computation capabilities through AI/ML-specific interfaces. Furthermore, NN accelerators reveal very few hardware design details, so applications cannot easily leverage the tensor operations NN accelerators provide. This paper introduces General-Purpose Computing on Edge Tensor Processing Units (GPTPU), an open-source, open-architecture framework that allows the developer and research communities to discover opportunities that NN accelerators enable for applications. GPTPU includes a powerful programming interface with efficient runtime system-level support -- similar to that of CUDA/OpenCL in GPGPU computing -- to bridge the gap between application demands and mismatched hardware/software interfaces. We built GPTPU machine uses Edge Tensor Processing Units (Edge TPUs), which are widely available and representative of many commercial NN accelerators. We identified several novel use cases and revisited the algorithms. By leveraging the underlying Edge TPUs to perform tensor-algorithm-based compute kernels, our results reveal that GPTPU can achieve a 2.46x speedup over high-end CPUs and reduce energy consumption by 40%.
Key facts. Cited by 5 papers in the map (data through 7 Oct 2026). First posted on arXiv 22 Jun 2021.
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Citing papers per year: 2023: 1; 2024: 3; 2025: 1.
5 papers.
- 2025Characterizing Mobile SoC for Accelerating Heterogeneous LLM Inferencecited by 20
- 2024LLM-Aided Compilation for Tensor Acceleratorscited by 8
- 2024Noise-Aware Training of Neuromorphic Dynamic Device Networkscited by 5
- 2024Flex-TPU: A Flexible TPU with Runtime Reconfigurable Dataflow Architecturecited by 1
- 2023Exploration of TPUs for AI Applicationscited by 0
- 2025Characterizing Mobile SoC for Accelerating Heterogeneous LLM Inference11 Jan 2025
- 2024LLM-Aided Compilation for Tensor Accelerators6 Aug 2024
- 2024Flex-TPU: A Flexible TPU with Runtime Reconfigurable Dataflow Architecture11 Jul 2024
- 2024Noise-Aware Training of Neuromorphic Dynamic Device Networks14 Jan 2024
- 2023Exploration of TPUs for AI Applications16 Sep 2023