mlsanityData to 7 Oct 2026

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication

arXiv 2106.10499 ↗First posted 19 Jun 2021cs.DC cs.AI cs.ARcited by 2

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Abstract (arXiv)

There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements (PEs) interacting via custom buffer hierarchies and networks-on-chip. The efficiency of these accelerators comes from employing optimized dataflow (i.e., spatial/temporal partitioning of data across the PEs and fine-grained scheduling) strategies to optimize data reuse. The focus of this work is to evaluate these accelerator architectures using a tiled general matrix-matrix multiplication (GEMM) kernel. To do so, we develop a framework that finds optimized mappings (dataflow and tile sizes) for a tiled GEMM for a given spatial accelerator and workload combination, leveraging an analytical cost model for runtime and energy. Our evaluations over five spatial accelerators demonstrate that the tiled GEMM mappings systematically generated by our framework achieve high performance on various GEMM workloads and accelerators.

Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 5 of its 43 references that are in the map. First posted on arXiv 19 Jun 2021.

Builds on

5 of 43 references.

References · 5

  1. 2015Deep Residual Learning for Image Recognitioncited by 51,809
  2. 2017In-Datacenter Performance Analysis of a Tensor Processing Unitcited by 610
  3. 2018Interstellar: Using Halide's Scheduling Language to Analyze DNN Acceleratorscited by 33
  4. 2020Fast Stencil-Code Computation on a Wafer-Scale Processorcited by 10
  5. 2019Understanding the Impact of On-chip Communication on DNN Accelerator Performancecited by 1

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Citing papers per year: 2021: 1; 2022: 0; 2023: 1.

2 papers.