ASSURE: RTL Locking Against an Untrusted Foundry
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Abstract (arXiv)
Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (IC) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: (i) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it obfuscates the semantics of an IC before logic synthesis; (iii) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE.
Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). First posted on arXiv 11 Oct 2020.
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Citing papers per year: 2021: 2; 2022: 0; 2023: 0; 2024: 0; 2025: 1.
3 papers.
- 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Codingcited by 11
- 2021Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attackscited by 3
- 2021Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunitiescited by 1
- 2025VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding17 Mar 2025
- 2021Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks19 Jul 2021
- 2021Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities5 Jul 2021