The gem5 Simulator: Version 20.0+
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Abstract (arXiv)
The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research. This simulation infrastructure allows researchers to model modern computer hardware at the cycle level, and it has enough fidelity to boot unmodified Linux-based operating systems and run full applications for multiple architectures including x86, Arm, and RISC-V. The gem5 simulator has been under active development over the last nine years since the original gem5 release. In this time, there have been over 7500 commits to the codebase from over 250 unique contributors which have improved the simulator by adding new features, fixing bugs, and increasing the code quality. In this paper, we give and overview of gem5's usage and features, describe the current state of the gem5 simulator, and enumerate the major changes since the initial release of gem5. We also discuss how the gem5 simulator has transitioned to a formal governance model to enable continued improvement and community support for the next 20 years of computer architecture research.
Key facts. Cited by 13 papers in the map (data through 7 Oct 2026). First posted on arXiv 7 Jul 2020.
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Citing papers per year: 2022: 1; 2023: 3; 2024: 3; 2025: 4; 2026: 2.
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- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Designcited by 6
- 2023PolyThrottle: Energy-efficient Neural Network Inference on Edge Devicescited by 5
- 2024A Digital Twin Framework for Liquid-cooled Supercomputers as Demonstrated at Exascalecited by 3
- 2025AI Benchmark Democratization and Carpentrycited by 3
- 2023Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architecturescited by 1
- 2022FullPack: Full Vector Utilization for Sub-Byte Quantized Inference on General Purpose CPUscited by 0
- 2024Accelerating Computer Architecture Simulation through Machine Learningcited by 0
- 2024Full-stack evaluation of Machine Learning inference workloads for RISC-V systemscited by 0
- 2025Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architecturescited by 0
- 2025OpenDPDv2: A Unified Learning and Optimization Framework for Neural Network Digital Predistortioncited by 0
- 2025Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processorscited by 0
- 2026OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocolcited by 0
1 more
- 2026PerfReasoning: How Well Do LLMs Reason on Hardware Performance?3 Sep 2026
- 2026OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocol27 May 2026
- 2025AI Benchmark Democratization and Carpentry12 Dec 2025
- 2025Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processors8 Oct 2025
- 2025OpenDPDv2: A Unified Learning and Optimization Framework for Neural Network Digital Predistortion9 Jul 2025
- 2025Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures14 Apr 2025
- 2024A Digital Twin Framework for Liquid-cooled Supercomputers as Demonstrated at Exascale7 Oct 2024
- 2024Full-stack evaluation of Machine Learning inference workloads for RISC-V systems24 May 2024
- 2024Accelerating Computer Architecture Simulation through Machine Learning28 Feb 2024
- 2023Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures20 Dec 2023
- 2023PolyThrottle: Energy-efficient Neural Network Inference on Edge Devices30 Oct 2023
- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design15 Jun 2023
- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Designcited by 6
- 2023PolyThrottle: Energy-efficient Neural Network Inference on Edge Devicescited by 5
- 2024A Digital Twin Framework for Liquid-cooled Supercomputers as Demonstrated at Exascalecited by 3
- 2025AI Benchmark Democratization and Carpentrycited by 3
- 2023Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architecturescited by 1
- 2022FullPack: Full Vector Utilization for Sub-Byte Quantized Inference on General Purpose CPUscited by 0
- 2024Accelerating Computer Architecture Simulation through Machine Learningcited by 0
- 2024Full-stack evaluation of Machine Learning inference workloads for RISC-V systemscited by 0
- 2025Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architecturescited by 0
- 2025OpenDPDv2: A Unified Learning and Optimization Framework for Neural Network Digital Predistortioncited by 0
- 2025Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processorscited by 0
- 2026OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocolcited by 0
- 2026OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocol27 May 2026
- 2025AI Benchmark Democratization and Carpentry12 Dec 2025
- 2025Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processors8 Oct 2025
- 2025OpenDPDv2: A Unified Learning and Optimization Framework for Neural Network Digital Predistortion9 Jul 2025
- 2025Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures14 Apr 2025
- 2024A Digital Twin Framework for Liquid-cooled Supercomputers as Demonstrated at Exascale7 Oct 2024
- 2024Full-stack evaluation of Machine Learning inference workloads for RISC-V systems24 May 2024
- 2024Accelerating Computer Architecture Simulation through Machine Learning28 Feb 2024
- 2023Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures20 Dec 2023
- 2023PolyThrottle: Energy-efficient Neural Network Inference on Edge Devices30 Oct 2023
- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design15 Jun 2023
- 2022FullPack: Full Vector Utilization for Sub-Byte Quantized Inference on General Purpose CPUs13 Nov 2022