A Simple Method to Reduce Off-chip Memory Accesses on Convolutional Neural Networks
Not on the map. Why?
Abstract (arXiv)
For convolutional neural networks, a simple algorithm to reduce off-chip memory accesses is proposed by maximally utilizing on-chip memory in a neural process unit. Especially, the algorithm provides an effective way to process a module which consists of multiple branches and a merge layer. For Inception-V3 on Samsung's NPU in Exynos, our evaluation shows that the proposed algorithm makes off-chip memory accesses reduced by 1/50, and accordingly achieves 97.59 % reduction in the amount of feature-map data to be transferred from/to off-chip memory.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). First posted on arXiv 28 Jan 2019.
Builds on
No reference list yet.
Built on by
Citing papers per year: 2023: 1.
1 paper.
- 2023Tensor Slicing and Optimization for Multicore NPUscited by 0
- 2023Tensor Slicing and Optimization for Multicore NPUs6 Apr 2023