MRAM Co-designed Processing-in-Memory CNN Accelerator for Mobile and IoT Applications
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Abstract (arXiv)
We designed a device for Convolution Neural Network applications with non-volatile MRAM memory and computing-in-memory co-designed architecture. It has been successfully fabricated using 22nm technology node CMOS Si process. More than 40MB MRAM density with 9.9TOPS/W are provided. It enables multiple models within one single chip for mobile and IoT device applications.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). First posted on arXiv 26 Nov 2018.
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Citing papers per year: 2021: 3; 2022: 0; 2023: 1; 2024: 1.
5 papers.
- 2021An improved LogNNet classifier for IoT applicationcited by 6
- 2021GnetSeg: Semantic Segmentation Model Optimized on a 224mW CNN Accelerator Chip at the Speed of 318FPScited by 1
- 2021GnetDet: Object Detection Optimized on a 224mW CNN Accelerator Chip at the Speed of 106FPScited by 1
- 2023Evaluation of STT-MRAM as a Scratchpad for Training in ML Acceleratorscited by 0
- 2024FLARE: FP-Less PTQ and Low-ENOB ADC Based AMS-PiM for Error-Resilient, Fast, and Efficient Transformer Accelerationcited by 0
- 2024FLARE: FP-Less PTQ and Low-ENOB ADC Based AMS-PiM for Error-Resilient, Fast, and Efficient Transformer Acceleration22 Nov 2024
- 2023Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators3 Aug 2023
- 2021An improved LogNNet classifier for IoT application30 May 2021
- 2021GnetDet: Object Detection Optimized on a 224mW CNN Accelerator Chip at the Speed of 106FPS19 Feb 2021
- 2021GnetSeg: Semantic Segmentation Model Optimized on a 224mW CNN Accelerator Chip at the Speed of 318FPS9 Jan 2021