Mini-batch Serialization: CNN Training with Inter-layer Data Reuse
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Abstract (arXiv)
Training convolutional neural networks (CNNs) requires intense computations and high memory bandwidth. We find that bandwidth today is over-provisioned because most memory accesses in CNN training can be eliminated by rearranging computation to better utilize on-chip buffers and avoid traffic resulting from large per-layer memory footprints. We introduce the MBS CNN training approach that significantly reduces memory traffic by partially serializing mini-batch processing across groups of layers. This optimizes reuse within on-chip buffers and balances both intra-layer and inter-layer reuse. We also introduce the WaveCore CNN training accelerator that effectively trains CNNs in the MBS approach with high functional-unit utilization. Combined, WaveCore and MBS reduce DRAM traffic by 75%, improve performance by 53%, and save 26% system energy for modern deep CNN training compared to conventional training mechanisms and accelerators.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). First posted on arXiv 30 Sep 2018.
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Citing papers per year: 2021: 4; 2022: 1; 2023: 2; 2024: 1.
8 papers.
- 2021Rethinking "Batch" in BatchNormcited by 44
- 2021GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descentcited by 9
- 2024BlockLLM: Multi-tenant Finer-grained Serving for Large Language Modelscited by 5
- 2023SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Acceleratorscited by 4
- 2021Towards Memory-Efficient Neural Networks via Multi-Level in situ Generationcited by 3
- 2021Optimizer Fusion: Efficient Training with Better Locality and Parallelismcited by 2
- 2022EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Acceleratorscited by 1
- 2023Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Acceleratorscited by 1
- 2024BlockLLM: Multi-tenant Finer-grained Serving for Large Language Models28 Apr 2024
- 2023SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Accelerators25 Jan 2023
- 2023Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Accelerators24 Jan 2023
- 2022EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators4 Feb 2022
- 2021Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation25 Aug 2021
- 2021Rethinking "Batch" in BatchNorm17 May 2021
- 2021Optimizer Fusion: Efficient Training with Better Locality and Parallelism1 Apr 2021
- 2021GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent15 Feb 2021