Input-Aware Auto-Tuning of Compute-Bound HPC Kernels
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Abstract (arXiv)
Efficient implementations of HPC applications for parallel architectures generally rely on external software packages (e.g., BLAS, LAPACK, CUDNN). While these libraries provide highly optimized routines for certain characteristics of inputs (e.g., square matrices), they generally do not retain optimal performance across the wide range of problems encountered in practice. In this paper, we present an input-aware auto-tuning framework for matrix multiplications and convolutions, ISAAC, which uses predictive modeling techniques to drive highly parameterized PTX code templates towards not only hardware-, but also application-specific kernels. Numerical experiments on the NVIDIA Maxwell and Pascal architectures show up to 3x performance gains over both cuBLAS and cuDNN after only a few hours of auto-tuning.
Key facts. Cited by 5 papers in the map (data through 7 Oct 2026). First posted on arXiv 15 Feb 2018.
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Citing papers per year: 2021: 1; 2022: 1; 2023: 0; 2024: 2; 2025: 0; 2026: 1.
5 papers.
- 2024CATS: Contextually-Aware Thresholding for Sparsity in Large Language Modelscited by 41
- 2024MGARD: A multigrid framework for high-performance, error-controlled data compression and refactoringcited by 8
- 2022Application Performance Modeling via Tensor Completioncited by 3
- 2021Using hardware performance counters to speed up autotuning convergence on GPUscited by 1
- 2026Hardware-Aware Features for CUTLASS Kernel Selectioncited by 0
- 2026Hardware-Aware Features for CUTLASS Kernel Selection28 Sep 2026
- 2024CATS: Contextually-Aware Thresholding for Sparsity in Large Language Models12 Apr 2024
- 2024MGARD: A multigrid framework for high-performance, error-controlled data compression and refactoring11 Jan 2024
- 2022Application Performance Modeling via Tensor Completion18 Oct 2022
- 2021Using hardware performance counters to speed up autotuning convergence on GPUs10 Feb 2021