# LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation

arXiv: https://arxiv.org/abs/2610.16625 · HTML: https://mlsanity.com/paper/2610.16625/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 20 of its 29 references that are in the map.
- First posted on arXiv 12 Oct 2026.

## Builds on (most cited first, 20 of 20)

- [ChatEDA: A Large Language Model Powered Autonomous Agent for EDA](https://mlsanity.com/paper/2308.10204/) (2023)
- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [A Survey of Research in Large Language Models for Electronic Design Automation](https://mlsanity.com/paper/2501.09655/) (2025)
- [ORFS-agent: Tool-Using Agents for Chip Design Optimization](https://mlsanity.com/paper/2506.08332/) (2025)
- [EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD](https://mlsanity.com/paper/2405.06676/) (2024)
- [EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit](https://mlsanity.com/paper/2509.25510/) (2025)
- [FlowTune: End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit](https://mlsanity.com/paper/2202.07721/) (2022)
- [Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement](https://mlsanity.com/paper/2604.14989/) (2026)
- [Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation](https://mlsanity.com/paper/2502.19091/) (2025)
- [PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM/VLM Agents for VLSI Physical Design](https://mlsanity.com/paper/2606.17253/) (2026)
- [Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph](https://mlsanity.com/paper/2504.11502/) (2025)
- [Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization](https://mlsanity.com/paper/2603.13767/) (2026)
- [Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours](https://mlsanity.com/paper/2605.05170/) (2026)
- [Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing](https://mlsanity.com/paper/2605.06936/) (2026)
- [Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction](https://mlsanity.com/paper/2308.03231/) (2023)
- [LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization](https://mlsanity.com/paper/2308.03233/) (2023)
- [Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs](https://mlsanity.com/paper/2512.00038/) (2025)
- [FluxEDA: A Unified Execution Infrastructure for Stateful Agentic EDA](https://mlsanity.com/paper/2603.25243/) (2026)
- [PACT: Post-route Agentic Checkpoint Tuning for FPGA Timing Closure](https://mlsanity.com/paper/2608.23602/) (2026)
- [LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration](https://mlsanity.com/paper/2608.27184/) (2026)

## Abstract (arXiv)

Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation. Across sixteen designs and seven LLMs, a single-iteration study compares three agent control granularities - expert-written recipes, direct EDA operations and LLM-constructed procedures - to ask how much control an agent needs per attempt. Functional-pass rates are 98.2%, 71.4% and 17.9%, respectively; yet direct operations give slightly larger 3.4% median Fmax gains when passing, versus 3.2% for recipes. This exposes a trade-off between execution reliability and timing improvement. Informed by this trade-off, a multi-iteration study fixes the action tier at expert recipes to ask how repeated attempts are best organised, comparing a fitted deterministic heuristic with sequential LLM reasoning, branching exploration and knowledge base-guided exploration within 12 checkpoints per run. Branching raises mean maximum-frequency improvement from 10.5% (sequential) to 16.0%, and the knowledge base to 20.3%, improving 15 of 16 designs. Characterisation across 2,421 recipe attempts profiled their gain and validation rates, showing hard-block re-placement gives the largest cumulative mean gain at 41.4MHz.