# LLM-Augmented Bayesian Optimization with Adaptive Policies for Chiplet Design Space Exploration

arXiv: https://arxiv.org/abs/2610.14612 · HTML: https://mlsanity.com/paper/2610.14612/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 8 of its 32 references that are in the map.
- First posted on arXiv 10 Oct 2026.

## Builds on (most cited first, 8 of 8)

- [Language Models are Few-Shot Learners](https://mlsanity.com/paper/2005.14165/) (2020)
- [Differentiable Expected Hypervolume Improvement for Parallel Multi-Objective Bayesian Optimization](https://mlsanity.com/paper/2006.05078/) (2020)
- [Large Language Models to Enhance Bayesian Optimization](https://mlsanity.com/paper/2402.03921/) (2024)
- [LLM-DSE: Searching Accelerator Parameters with LLM Agents](https://mlsanity.com/paper/2505.12188/) (2025)
- [FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning](https://mlsanity.com/paper/2011.13493/) (2020)
- [Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets](https://mlsanity.com/paper/2311.16417/) (2023)
- [MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures](https://mlsanity.com/paper/2410.09188/) (2024)
- [The Survey of Chiplet-based Integrated Architecture: An EDA perspective](https://mlsanity.com/paper/2411.04410/) (2024)

## Abstract (arXiv)

Chiplet technology is a key approach for extending Moore's Law. However, its design process is constrained by two primary challenges: the scarcity of early-stage platforms for rapidly evaluating chiplet-based heterogeneous systems, and the complex relationships between design parameters and optimization metrics. To address these challenges, we propose a synergistic framework that integrates a Large Language Model (LLM) with Bayesian Optimization (BO), enabling architectural-level simulation and automated optimization for the 2.5D/3D CPU-GPU heterogeneous chiplets. We extend the open-source chiplet simulator to evaluate 3D designs by supporting graph topologies. Further, to enhance the exploration efficiency of BO, we introduce an LLM that generates high-quality policies to guide the optimization process, enabled by our proposed adaptive directional policy reasoning (ADPR) and an exploration gain-aware fine-tuning method. Finally, we use the policy-guided BO to perform an automated and efficient exploration of the complex chiplet design space. Experiments on 2.5D and 3D chiplet reveal that our framework improves design space exploration efficiency.