# THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layout

arXiv: https://arxiv.org/abs/2609.35035 · HTML: https://mlsanity.com/paper/2609.35035/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 18 of its 40 references that are in the map.
- First posted on arXiv 28 Sep 2026.

## Builds on (most cited first, 18 of 18)

- [Expanding Performance Boundaries of Open-Source Multimodal Models with Model, Data, and Test-Time Scaling](https://mlsanity.com/paper/2412.05271/) (2024)
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- [Chip-Chat: Challenges and Opportunities in Conversational Hardware Design](https://mlsanity.com/paper/2305.13243/) (2023)
- [ChipGPT: How far are we from natural language hardware design](https://mlsanity.com/paper/2305.14019/) (2023)
- [ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models](https://mlsanity.com/paper/2406.18770/) (2024)
- [AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies](https://mlsanity.com/paper/2503.00205/) (2025)
- [DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks](https://mlsanity.com/paper/2110.00211/) (2021)
- [AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models](https://mlsanity.com/paper/2412.19824/) (2024)
- [DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent](https://mlsanity.com/paper/2412.05311/) (2024)
- [Enhancing Reasoning to Adapt Large Language Models for Domain-Specific Applications](https://mlsanity.com/paper/2502.04384/) (2025)
- [Post-Layout Simulation Driven Analog Circuit Sizing](https://mlsanity.com/paper/2310.14049/) (2023)
- [Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees](https://mlsanity.com/paper/2405.16951/) (2024)
- [Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2411.15212/) (2024)
- [Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search](https://mlsanity.com/paper/2505.05059/) (2025)
- [OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation](https://mlsanity.com/paper/2601.19439/) (2026)
- [A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces](https://mlsanity.com/paper/2402.19037/) (2024)
- [Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces Using Deep-Learning](https://mlsanity.com/paper/2408.06296/) (2024)

## Abstract (arXiv)

The integration of artificial intelligence into computer-aided design frameworks has sparked a shift in the design of analog integrated circuits (ICs), transitioning the field from using manual and algorithmic-based solutions to adopting automated and intelligent paradigms. In this scenario, the GDSII file represents the industry-standard database containing the ultimate and most accurate source of information of the analog circuit, encapsulating the complex physical geometries and parasitic realities that define tape out performance. This paper proposes THEIA, a novel dataset containing thousands of layout images paired with question-answer conversations, along with a benchmark that employs a fine-tuned vision-language model (VLM) to analyze GDSII files of analog circuits, enabling designers to interact with and query physical layouts as intuitive, meaningful entities. Experimental results using thousands of analog designs across five realistic tasks demonstrate that the proposed fine-tuned VLM outperforms state-of-the-art general-purpose VLMs by a significant margin (up to 73%), highlighting a fundamental gap between general-purpose multimodal reasoning and domain-specific layout understanding.