# K-TRAIL: Simulator-Guided Generative Design of EM/RF Circuits

arXiv: https://arxiv.org/abs/2609.23183 · HTML: https://mlsanity.com/paper/2609.23183/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 40 references that are in the map.
- First posted on arXiv 19 Sep 2026.

## Builds on (most cited first, 5 of 5)

- [Denoising Diffusion Probabilistic Models](https://mlsanity.com/paper/2006.11239/) (2020)
- [Denoising Diffusion Implicit Models](https://mlsanity.com/paper/2010.02502/) (2020)
- [Diffusion Posterior Sampling for General Noisy Inverse Problems](https://mlsanity.com/paper/2209.14687/) (2022)
- [Ensemble Kalman Diffusion Guidance: A Derivative-free Method for Inverse Problems](https://mlsanity.com/paper/2409.20175/) (2024)
- [Inverse Design of Multi-Layer Sub-Pixel-Resolution RF Passives Through Grayscale Diffusion with Flexible S-Parameter Conditioning](https://mlsanity.com/paper/2605.08233/) (2026)

## Built on by (most cited first, 1 of 1)

- [Simulator-Refined Diffusion for Radio-Frequency Inverse Design](https://mlsanity.com/paper/2609.38363/) (2026)

## Abstract (arXiv)

Inverse design of RF and electromagnetic (EM) circuits is challenging because the relationship between circuit layout and electrical response is non-unique, and full-wave simulation is computationally expensive. This paper presents K-TRAIL, a simulator-guided generative framework for automated EM/RF circuit synthesis. K-TRAIL combines diffusion-based layout generation with derivative-free ensemble Kalman guidance, allowing feedback from a black-box EM simulator to refine candidate layouts during generation without requiring adjoint sensitivities or differentiable solver models. The framework supports both synthesis from prescribed S-parameter responses and synthesis directly from RF performance constraints. Experiments on multi-layer RFIC structures show that simulator-guided generation improves agreement with target responses and can identify structurally distinct layouts that satisfy circuit-level design requirements. The proposed approach provides a practical path toward generative, verification-aware RF circuit design while retaining the flexibility to explore diverse layout topologies.