# RISC-V and machine learning: a survey

arXiv: https://arxiv.org/abs/2609.20677 · HTML: https://mlsanity.com/paper/2609.20677/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 27 of its 134 references that are in the map.
- First posted on arXiv 17 Sep 2026.

## Builds on (most cited first, 27 of 27)

- [FINN: A Framework for Fast, Scalable Binarized Neural Network Inference](https://mlsanity.com/paper/1612.07119/) (2016)
- [Fast inference of deep neural networks in FPGAs for particle physics](https://mlsanity.com/paper/1804.06913/) (2018)
- [Glow: Graph Lowering Compiler Techniques for Neural Networks](https://mlsanity.com/paper/1805.00907/) (2018)
- [TinyIREE: An ML Execution Environment for Embedded Systems from Compilation to Deployment](https://mlsanity.com/paper/2205.14479/) (2022)
- [Composable and Modular Code Generation in MLIR: A Structured and Retargetable Approach to Tensor Compiler Construction](https://mlsanity.com/paper/2202.03293/) (2022)
- [Compiler Support for Sparse Tensor Computations in MLIR](https://mlsanity.com/paper/2202.04305/) (2022)
- [GAP9Shield: A 150GOPS AI-capable Ultra-low Power Module for Vision and Ranging Applications on Nano-drones](https://mlsanity.com/paper/2407.13706/) (2024)
- [XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes](https://mlsanity.com/paper/2011.14325/) (2020)
- [DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training](https://mlsanity.com/paper/2303.17954/) (2023)
- [Locking Machine Learning Models into Hardware](https://mlsanity.com/paper/2405.20990/) (2024)
- [Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations](https://mlsanity.com/paper/2407.14274/) (2024)
- [LiteX: an open-source SoC builder and library based on Migen Python DSL](https://mlsanity.com/paper/2005.02506/) (2020)
- [xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems](https://mlsanity.com/paper/2405.19065/) (2024)
- [VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers](https://mlsanity.com/paper/2504.11227/) (2025)
- [Towards a high-performance AI compiler with upstream MLIR](https://mlsanity.com/paper/2404.15204/) (2024)
- [Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs](https://mlsanity.com/paper/2504.19659/) (2025)
- [A Survey on RISC-V Security: Hardware and Architecture](https://mlsanity.com/paper/2107.04175/) (2021)
- [HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC](https://mlsanity.com/paper/2211.14944/) (2022)
- [Lightweight Software Kernels and Hardware Extensions for Efficient Sparse Deep Neural Networks on Microcontrollers](https://mlsanity.com/paper/2503.06183/) (2025)
- [Support Vector Machines Classification on Bendable RISC-V](https://mlsanity.com/paper/2508.19656/) (2025)
- [A Chisel Framework for Flexible Design Space Exploration through a Functional Approach](https://mlsanity.com/paper/2302.12702/) (2023)
- [VEDLIoT -- Next generation accelerated AIoT systems and applications](https://mlsanity.com/paper/2305.05388/) (2023)
- [Challenges and Opportunities in the Co-design of Convolutions and RISC-V Vector Processors](https://mlsanity.com/paper/2311.05284/) (2023)
- [PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching](https://mlsanity.com/paper/2405.03217/) (2024)
- [On-Device Federated Continual Learning on RISC-V-based Ultra-Low-Power SoC for Intelligent Nano-Drone Swarms](https://mlsanity.com/paper/2503.17436/) (2025)
- [Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration](https://mlsanity.com/paper/2506.10921/) (2025)
- [MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI](https://mlsanity.com/paper/2508.01800/) (2025)

## Abstract (arXiv)

The intersection of open-source processor architectures and machine learning is driving the demand for customizable, efficient, and accessible hardware. This survey examines the state of the RISC-V ISA in machine learning applications, analyzing current capabilities, challenges, and future directions based on recent research. The analysis covers academic and commercial implementations, software frameworks, and real-world applications. The RISC-V machine learning ecosystem is evaluated, from instruction set extensions and core implementations to compiler optimizations and deployment strategies. Key contributions include a unified taxonomy of RISC-V ML implementations, a comparative analysis of performance and design trade-offs, an evaluation of software toolchain maturity, and the identification of emerging trends in instruction set extensions and specialized accelerators. Findings reveal progress in energy efficiency, specialized instruction development, and framework integration, while highlighting challenges in standardization, verification complexity, and ecosystem fragmentation. The analysis proposes four research directions to address current limitations: specialized neural processing extensions, adaptive and modular processor architectures, security frameworks, and energy-efficient multi-domain architectures. These directions provide a roadmap for advancing RISC-V as a foundational platform for next-generation machine learning systems.