# Detecting Soft Errors in Parallel Software with LLM-tuned Instruction Duplication

arXiv: https://arxiv.org/abs/2609.19531 · HTML: https://mlsanity.com/paper/2609.19531/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 10 of its 87 references that are in the map.
- First posted on arXiv 17 Sep 2026.

## Builds on (most cited first, 10 of 10)

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- [Can LLMs Reason with Rules? Logic Scaffolding for Stress-Testing and Improving LLMs](https://mlsanity.com/paper/2402.11442/) (2024)
- [Learning Accurate and Interpretable Decision Rule Sets from Neural Networks](https://mlsanity.com/paper/2103.02826/) (2021)
- [Quantifying OpenMP: Statistical Insights into Usage and Adoption](https://mlsanity.com/paper/2308.08002/) (2023)
- [Enabling Software Resilience in GPGPU Applications via Partial Thread Protection](https://mlsanity.com/paper/2103.02825/) (2021)
- [FlipTracker: Understanding Natural Error Resilience in HPC Applications](https://mlsanity.com/paper/1809.01362/) (2018)
- [Detection of Silent Data Corruptions in Smoothed Particle Hydrodynamics Simulations](https://mlsanity.com/paper/1904.10221/) (2019)
- [Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics](https://mlsanity.com/paper/2009.07985/) (2020)

## Abstract (arXiv)

We propose PaRID (PaRallel Instruction Duplication), a software-directed soft error detection framework that requires only compile-time effort for multithreading parallel programs. PaRID addresses two key challenges: supporting parallel programs with mixed serial and parallel regions and minimizing performance overhead without relying on costly dynamic profiling. It combines parallel-aware code transformation with LLM-tuned performance modeling, guided by eight generalizable findings from an offline characterization study, to enable fast soft error detection in parallel applications. Evaluation on NPB benchmarks shows that PaRID reduces protection overhead from 162.79% to 59.84% on average and achieves up to 5x speedup while maintaining full error detection effectiveness.