# REQAP: Resilient Weight Packing and Quantization for Edge DNN Acceleration

arXiv: https://arxiv.org/abs/2609.17555 · HTML: https://mlsanity.com/paper/2609.17555/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 7 of its 15 references that are in the map.
- First posted on arXiv 20 Jul 2026.

## Builds on (most cited first, 7 of 7)

- [Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference](https://mlsanity.com/paper/1712.05877/) (2017)
- [HAQ: Hardware-Aware Automated Quantization with Mixed Precision](https://mlsanity.com/paper/1811.08886/) (2018)
- [Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks](https://mlsanity.com/paper/1712.01507/) (2017)
- [DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators](https://mlsanity.com/paper/2303.08226/) (2023)
- [Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators](https://mlsanity.com/paper/2401.09509/) (2024)
- [AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators](https://mlsanity.com/paper/2403.02936/) (2024)
- [Fusion: A Framework for Unified Sequential Token AdaptatIon in VisiOn TraNsformers](https://mlsanity.com/paper/2607.02612/) (2026)

## Abstract (arXiv)

Efficient deployment of Deep Neural Networks (DNNs) on edge accelerators requires aggressive model compression while maintaining reliability in fault-prone hardware environments. This paper presents a reliability-aware quantized weight packing methodology for systolic-array-based DNN accelerators. A sensitivity-driven mixed-precision quantization framework assigns layer-wise bit-widths according to accuracy impact while enforcing symmetric precision between weights and activations. A deterministic register-level packing strategy consolidates multiple heterogeneous operand pairs into fixed-width register words, enabling SIMD-within-a-register (SWAR) style parallel execution that reduces both memory footprint and execution cycles. To improve resilience against hardware faults, selective bit-level protection replicates the most significant bits (MSBs) of critical layers into unused register space, achieving TMR-style protection with minimal overhead. A systolic-array simulation framework is developed to evaluate the proposed packing and fault-tolerance mechanisms under realistic execution conditions. Simulations in AlexNet, VGG-11, and ResNet-18 demonstrate up to 62% memory reduction and up to 56% reduction in Multiply-Accumulate (MAC) operations, while significantly improving accuracy resilience under fault injection compared to baseline and fully protected models.