# A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs

arXiv: https://arxiv.org/abs/2609.11713 · HTML: https://mlsanity.com/paper/2609.11713/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 3 of its 16 references that are in the map.
- First posted on arXiv 10 Sep 2026.

## Builds on (most cited first, 3 of 3)

- [Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator](https://mlsanity.com/paper/1707.09952/) (2017)
- [A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning](https://mlsanity.com/paper/1505.07814/) (2015)
- [Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits](https://mlsanity.com/paper/2406.19667/) (2024)

## Abstract (arXiv)

Artificial neural networks rely on vector-matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mitigate this bottleneck by performing in-memory, analog VMMs using memristive crossbar arrays. However, conventional current-mode readout circuits incur significant area and power overhead. This work proposes a fully analog readout architecture based on voltage-to-time conversion of the VMM output. By sensing the column voltage, the proposed approach avoids current-mode summing and scaling circuitry, improving area and energy efficiency. Post-layout simulations of a 10x1 SNN implemented in a 130 nm CMOS technology validate the proposed architecture, while application to a trained 64x10 SNN for digit classification further demonstrates its feasibility for SNN inference.