# VClare: Resolving Imperfect Specifications in LLM-Based Verilog Generation

arXiv: https://arxiv.org/abs/2607.24854 · HTML: https://mlsanity.com/paper/2607.24854/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 25 Jul 2026.

## Built on by (most cited first, 1 of 1)

- [SpecRead: A Benchmark for Measuring Whether Language Models Understand Hardware Specifications](https://mlsanity.com/paper/2609.33699/) (2026)

## Abstract (arXiv)

Large language models (LLMs) have demonstrated promising capabilities in generating Verilog code from natural language specifications. However, human-written specifications often contain semantic imperfections such as vagueness, contradictions, and incompleteness, which can significantly degrade the quality of hardware design generated by LLMs. In this paper, we present the first systematic study of imperfect specifications and propose an automated framework VClare to repair them to enhance the quality of resulting Verilog design. The proposed framework explores two complementary repair paradigms. The textitSpec-Level Repair conducts LLM-driven inconsistency mining directly on the specification texts, while the textitSim-Level Repair employs simulation-based behavioral clustering with optional test-time inconsistency arbitration. In addition, we propose two new benchmark datasets with systematically injected specification defects. The first benchmark dataset is derived from the VerilogEval-human benchmark targeting single-module tasks, while the other benchmark dataset is derived from the ComplexVDB dataset and contains 53 multi-module tasks that reflect more realistic engineering scenarios. For single-module tasks, the VClare framework can repair the imperfections in the specifications effectively and thus enhance the pass rate of the generated Verilog design by 12.7%, while for the multi-module tasks this enhancement can reach 13.7%, demonstrating the capabilities of specification repair by VClare as well as further potential of LLMs in front-end hardware design.footnoteThe two benchmark datasets are released at https://anonymous.4open.science/r/VClare/.