# NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

arXiv: https://arxiv.org/abs/2607.15123 · HTML: https://mlsanity.com/paper/2607.15123/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 8 of its 23 references that are in the map.
- First posted on arXiv 16 Jul 2026.

## Builds on (most cited first, 8 of 8)

- [Attention Is All You Need](https://mlsanity.com/paper/1706.03762/) (2017)
- [M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs](https://mlsanity.com/paper/2311.02758/) (2023)
- [Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration](https://mlsanity.com/paper/2502.03763/) (2025)
- [CoMeFa: Compute-in-Memory Blocks for FPGAs](https://mlsanity.com/paper/2203.12521/) (2022)
- [BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs](https://mlsanity.com/paper/2304.03974/) (2023)
- [Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research](https://mlsanity.com/paper/2106.07087/) (2021)
- [RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration](https://mlsanity.com/paper/2312.06532/) (2023)
- [NL-DPE: An Analog In-memory Non-Linear Dot Product Engine for Efficient CNN and LLM Inference](https://mlsanity.com/paper/2511.13950/) (2025)

## Abstract (arXiv)

Recent FPGAs have improved deep learning (DL) inference efficiency through dedicated tensor blocks and in-BRAM computation. ReRAM-based analog in-memory computing (IMC) pushes efficiency further, offering an order-of-magnitude improvement in compute density and energy efficiency over conventional digital logic by performing vector-matrix multiplication (VMM) directly within the ReRAM crossbar; prior work has integrated such IMC blocks into FPGAs for DL inference. However, conventional IMC designs support only static-weight VMM, leaving nonlinear operations and dynamic matrix-matrix multiplication (DIMM) to the FPGA fabric. As a result, the benefits of IMC are largely confined to static-weight models, whereas Transformer-based models, which rely on frequent nonlinear and DIMM operations, gain only limited improvement. Moreover, the ADCs within each IMC block consume more than 70% of its area and power, further limiting system efficiency and scalability. To address these limitations, we propose a novel FPGA architecture that integrates an ADC-free IMC block, replacing the conventional ADC with analog content-addressable memories (ACAMs) that natively perform nonlinear operations inside the block. To fully exploit this block, we conduct an FPGA-aware design-space exploration that determines optimal crossbar dimensions while balancing FPGA area, flexibility, and DL performance, and we develop an efficient mapping that leverages ACAMs to carry out DIMM operations, extending the applicability of IMC to attention computation. On CNN and Transformer-based benchmarks, the proposed architecture achieves up to 40x and 1.9x higher energy efficiency and 4.1x and 2.5x higher area efficiency, respectively. Overall, it significantly improves FPGA DL inference efficiency and sustains robust gains on Transformer-based workloads across long input sequences, advancing domain-specialized FPGA design.