# Arithmetic Packing on Wide Integer Datapaths in DSP Primitives of Modern FPGA Devices

arXiv: https://arxiv.org/abs/2606.11065 · HTML: https://mlsanity.com/paper/2606.11065/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 5 of its 18 references that are in the map.
- First posted on arXiv 9 Jun 2026.

## Builds on (most cited first, 5 of 5)

- [The Computational Limits of Deep Learning](https://mlsanity.com/paper/2007.05558/) (2020)
- [FINN: A Framework for Fast, Scalable Binarized Neural Network Inference](https://mlsanity.com/paper/1612.07119/) (2016)
- [HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation](https://mlsanity.com/paper/2112.13972/) (2021)
- [Field-Programmable Gate Array Architecture for Deep Learning: Survey & Future Directions](https://mlsanity.com/paper/2404.10076/) (2024)
- [DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks](https://mlsanity.com/paper/2203.11028/) (2022)

## Abstract (arXiv)

Deep Neural Networks increasingly employ low-precision quantization to reduce computational requirements. While FPGAs are well suited for workloads with heterogeneous precisions, their dedicated digital signal processing (DSP) slices only feature fixed-width datapaths that are significantly underutilized by low-bitwidth arithmetic. While previous approaches have already introduced the packing of multiple values onto the same wide DSP datapath, they either only support specific fixed bitwidths or are wasteful regarding the use of additional support logic external to the DSP. This paper proposes an efficient method to dynamically pack multiple (un-)signed inputs with arbitrary bitwidths into a wide multiplier path by leveraging the DSP's internal pre-adder. Building on this, we present two distinct architectures, one optimized for matrix-vector multiplications and the other for convolutions. Our implementations are integrated into AMD's FINN framework. With these optimizations, we reduce the LUT utilization by 21% and increase the FPS/DSP by 36% for the UltraNet model compared to the FINN reference.