# SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC

arXiv: https://arxiv.org/abs/2606.09946 · HTML: https://mlsanity.com/paper/2606.09946/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 11 of its 44 references that are in the map.
- First posted on arXiv 8 Jun 2026.

## Builds on (most cited first, 11 of 11)

- [NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps](https://mlsanity.com/paper/1706.01406/) (2017)
- [An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs](https://mlsanity.com/paper/2001.01955/) (2020)
- [Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads](https://mlsanity.com/paper/2412.11702/) (2024)
- [ShortcutFusion: From Tensorflow to FPGA-based accelerator with reuse-aware memory allocation for shortcut data](https://mlsanity.com/paper/2106.08167/) (2021)
- [Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques](https://mlsanity.com/paper/2307.11124/) (2023)
- [A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits](https://mlsanity.com/paper/2301.12181/) (2023)
- [HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator](https://mlsanity.com/paper/2409.04976/) (2024)
- [HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing](https://mlsanity.com/paper/2410.20150/) (2024)
- [SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency](https://mlsanity.com/paper/2601.17279/) (2026)
- [CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications](https://mlsanity.com/paper/2602.19268/) (2026)
- [CARMEN: CORDIC-Accelerated Resource-Efficient Multi-Precision Inference Engine for Deep Learning](https://mlsanity.com/paper/2605.06878/) (2026)

## Abstract (arXiv)

Edge-AI systems increasingly require real-time CNN inference under strict energy, performance, security, and privacy constraints. Approximate computing improves hardware efficiency by exploiting the error resilience of neural network workloads; however, most approximate CNN accelerators do not jointly consider secure, privacy-aware edge deployment. This paper presents SPARX, a Secure and Privacy-Aware Approximate CNN Acceleration framework integrated within a heterogeneous RV32IMC RISC-V System-on-Chip (SoC). SPARX combines a custom RISC-V instruction extension, an approximate logarithmic CNN acceleration unit, a lightweight differential-noise-based privacy engine, and a challenge-response authentication mechanism. To guide arithmetic selection, an approximation-aware decision framework is introduced that uses the Approximation Severity Index (ASI), Approximation Efficiency (AE), Quality of Approximation (QoA), Approximation Figure-of-Merit (AFOM), and Hardware Acceleration Efficiency (HAE). Evaluation across 11 state-of-the-art approximate MAC architectures identifies the Iterative Logarithmic Multiplier (ILM) as the most suitable design, achieving 51.7% area reduction, 81.5% power reduction, and 2.13x throughput improvement compared with an accurate radix-4 Booth MAC, while only reducing ResNet-20/CIFAR-10 accuracy by 2.82 percentage points. FPGA implementation on a Xilinx VC707 platform achieves 58.4 GOPS/W energy efficiency at 250 MHz, while 28-nm CMOS physical implementation validates ASIC feasibility