# FP8 is All You Need (Part 1): Debunking Hardware FP64 as the HPC Holy Grail (Sep 3rd version)

arXiv: https://arxiv.org/abs/2606.06510 · HTML: https://mlsanity.com/paper/2606.06510/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 9 of its 57 references that are in the map.
- First posted on arXiv 28 May 2026.

## Builds on (most cited first, 9 of 9)

- [DeepSeek-V3 Technical Report](https://mlsanity.com/paper/2412.19437/) (2024)
- [FP8 Formats for Deep Learning](https://mlsanity.com/paper/2209.05433/) (2022)
- [Pretraining Large Language Models with NVFP4](https://mlsanity.com/paper/2509.25149/) (2025)
- [Guaranteed DGEMM Accuracy While Using Reduced Precision Tensor Cores Through Extensions of the Ozaki Scheme](https://mlsanity.com/paper/2511.13778/) (2025)
- [Double-Precision Matrix Multiplication Emulation via Ozaki-II Scheme with FP8 Quantization](https://mlsanity.com/paper/2603.10634/) (2026)
- [High-performance sparse matrix-matrix products on Intel KNL and multicore architectures](https://mlsanity.com/paper/1804.01698/) (2018)
- [SPIDER: Unleashing Sparse Tensor Cores for Stencil Computation via Strided Swapping](https://mlsanity.com/paper/2506.22035/) (2025)
- [SparStencil: Retargeting Sparse Tensor Cores to Scientific Stencil Computations via Structured Sparsity Transformation](https://mlsanity.com/paper/2506.22969/) (2025)
- [Error Analysis of Matrix Multiplication Emulation Using Ozaki-II Scheme](https://mlsanity.com/paper/2602.02549/) (2026)

## Built on by (most cited first, 1 of 1)

- [The Missing Fourth Term for the Emulation Tensor Memory Equilibrium (TME) Model: The Residue Deconstruction Cost](https://mlsanity.com/paper/2610.10924/) (2026)

## Abstract (arXiv)

We argue that on AI-optimised GPUs of the NVIDIA B300 generation and beyond, the FP8 tensor-core matrix operation, composed through CRT-based Ozaki Scheme II, can serve as the dominant matrix-work substrate for the surveyed matrix-dominated FP64 kernel classes at FP64-grade accuracy, with native FP64 recast from a hardware requirement into a derived accuracy guarantee. The claim is conditional: the FP8 op is the candidate dominant multiplication substrate, with a bounded auxiliary set of integer deconstruction/reconstruction work, FP32/Kulisch reductions, data movement and a native-FP64 fallback, organised as a hierarchy from the FP8 op through Ozaki II and the Berkeley dwarfs to applications. The instrument is the Tensor-Memory Equilibrium (TME) model, a Roofline extension with four parameters (compute multiplier α=3r+1, bandwidth multiplier β, reconstruction cost γ, and the per-input deconstruction cost cq identified in an NVIDIA review) under which, at its upper bound, the reduction to FP8 costs no performance against an ideal native-FP64 machine of equal bandwidth. On-chip tile fusion drives β → 1; the deconstruction term sets a threshold intensity below which emulation is conversion-bound. At the fused, engineered-cq bound every surveyed class reaches the memory roof, with two priced exceptions: large dense-square DGEMM sits at a deconstruction floor near 0.50 of the FP8 arithmetic roof (about 235 of 473 TFLOPS on the NVIDIA Rubin GPU), a liftable co-design coordinate, and the 3-D FFT is walled by a per-output integer epilogue at 4.9-6.7× its roof in software, recoverable with minor hardware and one moderate ask. Ozaki II lifts the emulated FP64 ceiling from ≈ 1.3 to ≈ 135 TFLOPS on B300 and ≈ 473 on Rubin; three deconstruction-path hardware options are given; constants are engine-checked.