# OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocol

arXiv: https://arxiv.org/abs/2605.28717 · HTML: https://mlsanity.com/paper/2605.28717/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 6 of its 59 references that are in the map.
- First posted on arXiv 27 May 2026.

## Builds on (most cited first, 6 of 6)

- [The gem5 Simulator: Version 20.0+](https://mlsanity.com/paper/2007.03152/) (2020)
- [Revisiting Network Support for RDMA](https://mlsanity.com/paper/1806.08159/) (2018)
- [Effectively Prefetching Remote Memory with Leap](https://mlsanity.com/paper/1911.09829/) (2019)
- [Collie: Finding Performance Anomalies in RDMA Subsystems](https://mlsanity.com/paper/2304.11467/) (2023)
- [STrack: A Reliable Multipath Transport for AI/ML Clusters](https://mlsanity.com/paper/2407.15266/) (2024)
- [Clio: A Hardware-Software Co-Designed Disaggregated Memory System](https://mlsanity.com/paper/2108.03492/) (2021)

## Abstract (arXiv)

Modern datacenter RDMA is bottlenecked at the network interface, not the wire. A NIC running RoCE or InfiniBand holds per-connection state for every (application, remote-endpoint) pair - hundreds of megabytes at 1024-application fanout - and pays a four-traversal PCIe round trip on a 64-byte operation, inflating latency an order of magnitude beyond the wire. Both follow from the Queue Pair over PCIe abstraction RDMA inherits from InfiniBand. Huawei's Unified Bus (UB), a public 2025 specification, changes the abstraction: it decouples per-application endpoint state from per-host transport state so connection context grows additively, exposes ordering as opt-in, and reaches remote memory through native CPU load/store to an on-chip-bus controller. UB ships in Huawei's closed Ascend 950 silicon. OpenURMA is the first clean-room open implementation of UB's transport and transaction layers, realised at three tiers - synthesisable RTL on Alveo U50, a cycle-level two-node SystemC simulator, and a gem5 full-system scaffold - each with a matched OpenRoCE (RoCEv2 RC) baseline. The contribution is the implementation, harness, and controlled comparison closed silicon does not admit. On the canonical 64-byte remote fetch - LOAD on UB-spec Sec.8.3, READ on RoCEv2 RC - UB's load/store path delivers ~500 ns end-to-end, 4.37x below the matched baseline (2186 ns), sustains 2.80x higher throughput, and fits in ~14% of a U50's LUTs.