# FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors

arXiv: https://arxiv.org/abs/2605.08594 · HTML: https://mlsanity.com/paper/2605.08594/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 15 of its 51 references that are in the map.
- First posted on arXiv 9 May 2026.

## Builds on (most cited first, 15 of 15)

- [Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks](https://mlsanity.com/paper/1906.01017/) (2019)
- [FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation](https://mlsanity.com/paper/1912.00941/) (2019)
- [Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator](https://mlsanity.com/paper/1802.04657/) (2018)
- [Silent Data Corruptions at Scale](https://mlsanity.com/paper/2102.11245/) (2021)
- [SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis](https://mlsanity.com/paper/2504.15377/) (2025)
- [A Low-cost Strategic Monitoring Approach for Scalable and Interpretable Error Detection in Deep Neural Networks](https://mlsanity.com/paper/2310.20349/) (2023)
- [BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems](https://mlsanity.com/paper/2307.10041/) (2023)
- [SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators](https://mlsanity.com/paper/2403.02946/) (2024)
- [ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance](https://mlsanity.com/paper/2503.24053/) (2025)
- [ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Neural Network Processing](https://mlsanity.com/paper/2302.10469/) (2023)
- [ALBERTA: ALgorithm-Based Error Resilience in Transformer Architectures](https://mlsanity.com/paper/2310.03841/) (2023)
- [CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design](https://mlsanity.com/paper/2503.01162/) (2025)
- [PVF:Understanding AI Vulnerability Against SDCs](https://mlsanity.com/paper/2405.01741/) (2024)
- [FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference](https://mlsanity.com/paper/2503.04426/) (2025)
- [Periodic Online Testing for Sparse Systolic Tensor Arrays](https://mlsanity.com/paper/2504.18628/) (2025)

## Built on by (most cited first, 1 of 1)

- [Syndrome Decoding for Silent Data Corruption in Quantized Integer GPU Arithmetic](https://mlsanity.com/paper/2609.19743/) (2026)

## Abstract (arXiv)

Systolic arrays are the dominant compute fabric for neural network inference. Prior work has addressed column-level fault detection efficiently with uniform test patterns, but row-level (PE-level) fault localization within a faulty column remains open without resorting to hardware redundancy. The fundamental obstacle is that uniform test inputs destroy per-row signatures: any test that activates every row equally cannot distinguish which row is the source of an observed deviation. In this paper, we propose a lightweight, purely algorithmic remedy based on coprime test vectors. By assigning pairwise coprime integers as test-input entries, a permanent weight-register fault produces a deviation whose divisibility signature uniquely identifies the faulty row. Under a general bounded error model, a single test pass localizes the faulty row with high probability. This error model covers a broader class of faults than what prior dataflow-aware testing work has primarily emphasized. When one round is insufficient, a second pass using a ratio computation achieves exact localization; for the special case of single-bit errors, odd coprime entries guarantee exact localization in one round. For INT16 arithmetic, a single test pass covers array sizes up to 256×256 with localization probability above 0.98, at a test cost under 1% of one inference GEMM tile.