# Effective and Memory-Efficient Alternatives to ECC for Reliable Large-Scale DNNs

arXiv: https://arxiv.org/abs/2605.07417 · HTML: https://mlsanity.com/paper/2605.07417/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 7 of its 32 references that are in the map.
- First posted on arXiv 8 May 2026.

## Builds on (most cited first, 7 of 7)

- [Scaling Vision Transformers](https://mlsanity.com/paper/2106.04560/) (2021)
- [In-Datacenter Performance Analysis of a Tensor Processing Unit](https://mlsanity.com/paper/1704.04760/) (2017)
- [Silent Data Corruptions at Scale](https://mlsanity.com/paper/2102.11245/) (2021)
- [A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks](https://mlsanity.com/paper/2305.05750/) (2023)
- [Soft Error Reliability Analysis of Vision Transformers](https://mlsanity.com/paper/2302.10468/) (2023)
- [In-Place Zero-Space Memory Protection for CNN](https://mlsanity.com/paper/1910.14479/) (2019)
- [Functional Error Correction for Robust Neural Networks](https://mlsanity.com/paper/2001.03814/) (2020)

## Built on by (most cited first, 2 of 2)

- [CheckOne: Lightweight Fault Detection and Mitigation for Vision Transformers](https://mlsanity.com/paper/2608.04035/) (2026)
- [BLADE: ReliaBle Dynamic Hardware-Aware SNN-ANN Boundary SeLection for Event-BAseD Object DEtection](https://mlsanity.com/paper/2609.17562/) (2026)

## Abstract (arXiv)

Modern Deep Learning (DL) workloads are increasingly deployed in safety-critical domains, such as automotive systems and hyperscale data centers, where transient hardware faults pose a serious threat to system reliability. These workloads are highly memory-intensive, and their correct functionality strongly depends on model parameters stored in memory, which are typically protected using Error Correction Codes (ECCs). In this work, we study ECC's impact on such models and propose two lightweight alternatives to ECCs that achieve superior reliability. The first approach, MSET, selectively hardens the most vulnerable bits in CNN and ViT parameters, while the second approach, CEP, provides fine-grained protection for all parameter bits. Experimental results demonstrate that both methods significantly enhance the reliability of large CNNs and ViTs, mostly outperforming conventional Single Error Detection Double Error Correction (SECDED) ECC schemes, with no memory overhead and, in fact, with considerably lower area and delay characteristics when compared to SECDEC. Experimental results indicate that ViTs can be effectively protected by merely protecting their highest exponent bits in FP16 and FP32 representations. Furthermore, applying the CEP technique can guarantee the resilience of DNNs by up to one order of magnitude higher BERs, with a 3.5x lower area overhead and 7x faster decoder compared to SECDED ECC.