# LLM-Driven Design Space Exploration of FPGA-based Accelerators

arXiv: https://arxiv.org/abs/2605.05920 · HTML: https://mlsanity.com/paper/2605.05920/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 14 references that are in the map.
- First posted on arXiv 7 May 2026.

## Builds on (most cited first, 5 of 5)

- [From Automation to Autonomy: A Survey on Large Language Models in Scientific Discovery](https://mlsanity.com/paper/2505.13259/) (2025)
- [SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference](https://mlsanity.com/paper/2110.00478/) (2021)
- [iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs](https://mlsanity.com/paper/2505.22086/) (2025)
- [Field-Programmable Gate Array Architecture for Deep Learning: Survey & Future Directions](https://mlsanity.com/paper/2404.10076/) (2024)
- [LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Exploration](https://mlsanity.com/paper/2503.13301/) (2025)

## Built on by (most cited first, 1 of 1)

- [Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA](https://mlsanity.com/paper/2606.11117/) (2026)

## Abstract (arXiv)

Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, alongside a feedback loop that enables reinforced fine-tuning for continuous improvement. We demonstrate the feasibility of SECDA-DSE through an initial high-level synthesis based evaluation of a generated accelerator design that meets synthesis timing and resource constraints on an Zynq-7000 FPGA.