# VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog

arXiv: https://arxiv.org/abs/2604.15375 · HTML: https://mlsanity.com/paper/2604.15375/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 12 of its 27 references that are in the map.
- First posted on arXiv 15 Apr 2026.

## Builds on (most cited first, 12 of 12)

- [Large Language Model for Vulnerability Detection: Emerging Results and Future Directions](https://mlsanity.com/paper/2401.15468/) (2024)
- [LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust](https://mlsanity.com/paper/2405.07061/) (2024)
- [LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debugging](https://mlsanity.com/paper/2401.16448/) (2024)
- [All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification](https://mlsanity.com/paper/2403.16750/) (2024)
- [Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verification](https://mlsanity.com/paper/2405.12347/) (2024)
- [TrojanLoC: LLM-based Framework for RTL Trojan Localization](https://mlsanity.com/paper/2512.00591/) (2025)
- [BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection](https://mlsanity.com/paper/2505.22878/) (2025)
- [LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs](https://mlsanity.com/paper/2504.21770/) (2025)
- [Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design](https://mlsanity.com/paper/2209.01291/) (2022)
- [VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code](https://mlsanity.com/paper/2506.07239/) (2025)
- [Security Properties for Open-Source Hardware Designs](https://mlsanity.com/paper/2412.08769/) (2024)
- [VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog](https://mlsanity.com/paper/2508.13092/) (2025)

## Built on by (most cited first, 2 of 2)

- [LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges](https://mlsanity.com/paper/2605.10807/) (2026)
- [Hardware Design and Security in the Era of Chiplets and LLMs](https://mlsanity.com/paper/2608.05063/) (2026)

## Abstract (arXiv)

Large Language Models (LLMs) have shown significant improvement in RTL code generation. Despite the advances, the generated code is often riddled with common vulnerabilities and weaknesses (CWEs) that can slip by untrained eyes. Attackers can often exploit these weaknesses to fulfill their nefarious motives. Existing RTL bug-detection techniques rely on rule-based checks, formal properties, or coarse-grained structural analysis, which either fail to capture semantic vulnerabilities or lack precise localization. In our work, we bridge this gap by proposing an embedding-based bug-detection framework that detects and classifies bugs at both module and line-level granularity. Our method achieves about 89% precision in identifying common CWEs such as CWE-1244 and CWE-1245, and 96% accuracy in detecting line-level bugs.