# Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection

arXiv: https://arxiv.org/abs/2604.13298 · HTML: https://mlsanity.com/paper/2604.13298/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- Placed in Agent threats, guardrails and governance, one of 16 directions in LLM agents and tool use.
- Builds on 20 of its 40 references that are in the map.
- First posted on arXiv 14 Apr 2026.

## Placed in

- LLM agents and tool use / [Agent threats, guardrails and governance](https://mlsanity.com/agents/agent-threats-guardrails-and-governance/)

## Builds on (most cited first, 20 of 20)

- [VeriGen: A Large Language Model for Verilog Code Generation](https://mlsanity.com/paper/2308.00708/) (2023)
- [Chip-Chat: Challenges and Opportunities in Conversational Hardware Design](https://mlsanity.com/paper/2305.13243/) (2023)
- [RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models](https://mlsanity.com/paper/2311.16543/) (2023)
- [SagaLLM: Context Management, Validation, and Transaction Guarantees for Multi-Agent LLM Planning](https://mlsanity.com/paper/2503.11951/) (2025)
- [Formal-LLM: Integrating Formal Language and Natural Language for Controllable LLM-based Agents](https://mlsanity.com/paper/2402.00798/) (2024)
- [Flow: Modularized Agentic Workflow Automation](https://mlsanity.com/paper/2501.07834/) (2025)
- [AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs](https://mlsanity.com/paper/2402.00386/) (2024)
- [HDLdebugger: Streamlining HDL debugging with Large Language Models](https://mlsanity.com/paper/2403.11671/) (2024)
- [ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation](https://mlsanity.com/paper/2402.00093/) (2024)
- [Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis](https://mlsanity.com/paper/2312.01022/) (2023)
- [Self-Organizing Agent Network for LLM-based Workflow Automation](https://mlsanity.com/paper/2508.13732/) (2025)
- [Robust Planning with Compound LLM Architectures: An LLM-Modulo Approach](https://mlsanity.com/paper/2411.14484/) (2024)
- [HW-V2W-Map: Hardware Vulnerability to Weakness Mapping Framework for Root Cause Analysis with GPT-assisted Mitigation Suggestion](https://mlsanity.com/paper/2312.13530/) (2023)
- [SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions](https://mlsanity.com/paper/2407.12352/) (2024)
- [Large Language Models and Attention-Based AI for Hardware Design and Security: Progress, Challenges, and Opportunities](https://mlsanity.com/paper/2504.08854/) (2025)
- [Automated Hardware Logic Obfuscation Framework Using GPT](https://mlsanity.com/paper/2405.12197/) (2024)
- [Transformers for Secure Hardware Systems: Applications, Challenges, and Outlook](https://mlsanity.com/paper/2505.22605/) (2025)
- [LLM-HyPZ: Hardware Vulnerability Discovery using an LLM-Assisted Hybrid Platform for Zero-Shot Knowledge Extraction and Refinement](https://mlsanity.com/paper/2509.00647/) (2025)
- [CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks](https://mlsanity.com/paper/2401.07142/) (2024)
- [SubLock: Sub-Circuit Replacement based Input Dependent Key-based Logic Locking for Robust IP Protection](https://mlsanity.com/paper/2406.19091/) (2024)

## Built on by (most cited first, 3 of 3)

- [LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges](https://mlsanity.com/paper/2605.10807/) (2026)
- [VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification](https://mlsanity.com/paper/2607.01668/) (2026)
- [Hardware Design and Security in the Era of Chiplets and LLMs](https://mlsanity.com/paper/2608.05063/) (2026)

## Abstract (arXiv)

The globalization of integrated circuit (IC) design and manufacturing has increased the exposure of hardware intellectual property (IP) to untrusted stages of the supply chain, raising concerns about reverse engineering, piracy, tampering, and overbuilding. Hardware netlist obfuscation is a promising countermeasure, but automating the generation of functionally correct and security-relevant obfuscated circuits remains challenging, particularly for benchmark-scale designs. This paper presents an agentic, large language model (LLM)-driven framework for automated hardware netlist obfuscation. The proposed framework combines retrieval-grounded planning, structured lock-plan generation, deterministic netlist compilation, functional verification, and SAT-based security evaluation. Rather than a single prompt-to-output generation step, the framework decomposes the task into specialized stages for circuit analysis, synthesis, verification, and attack evaluation. We evaluate the framework on ISCAS-85 benchmarks using functional equivalence checking and SAT-based attacks. Results show that the framework generates correct locked netlists while introducing measurable output corruption under incorrect keys, while SAT attacks remain effective. These findings highlight both the potential and current limitations of agentic LLM-driven obfuscation.