# Assertain: Automated Security Assertion Generation Using Large Language Models

arXiv: https://arxiv.org/abs/2604.01583 · HTML: https://mlsanity.com/paper/2604.01583/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 2 Apr 2026.

## Built on by (most cited first, 1 of 1)

- [VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification](https://mlsanity.com/paper/2607.01668/) (2026)

## Abstract (arXiv)

The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property verification. This paper presents Assertain, an automated framework that integrates RTL design analysis, Common Weakness Enumeration (CWE) mapping, and threat model intelligence to automatically generate security properties and executable SystemVerilog Assertions. Assertain leverages large language models with a self-reflection refinement mechanism to ensure both syntactic correctness and semantic consistency. Evaluated on 11 representative hardware designs, Assertain outperforms GPT-5 by 61.22%, 59.49%, and 67.92% in correct assertion generation, unique CWE coverage, and architectural flaw detection, respectively. These results demonstrate that Assertain significantly expands vulnerability coverage, improves assertion quality, and reduces manual effort in hardware security verification.