# Beating vDSP: A 138 GFLOPS Radix-8 Stockham FFT on Apple Silicon via Two-Tier Register-Threadgroup Memory Decomposition

arXiv: https://arxiv.org/abs/2603.27569 · HTML: https://mlsanity.com/paper/2603.27569/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 29 Mar 2026.

## Built on by (most cited first, 1 of 1)

- [When Quantization Is Free: An int4 KV Cache That Outruns fp16 on Apple Silicon](https://mlsanity.com/paper/2605.05699/) (2026)

## Abstract (arXiv)

We present an optimized Fast Fourier Transform (FFT) implementation for Apple Silicon GPUs, achieving 138.45~GFLOPS for N!=!4096 complex single-precision transforms -- a 29% improvement over Apple's highly optimized vDSP/Accelerate baseline (107~GFLOPS). Our approach is grounded in a two-tier local memory model that formally characterizes the Apple GPU's 208~KiB register file as the primary data-resident tier and the 32~KiB threadgroup memory as an exchange-only tier, extending the decomposition framework established in a 2015 PhD thesis on Intel integrated GPU FFT for radar processing. We implement and evaluate radix-4 and radix-8 split-radix Stockham kernels in Metal Shading Language (MSL), demonstrating that the radix-8 decimation-in-time butterfly with 512 threads yields the best performance. We further present the first investigation of Apple's textttsimdgroupmatrix 8×8 hardware MMA for FFT butterfly computation and report the counter-intuitive finding that on Apple GPU, threadgroup memory barriers are inexpensive (~2 cycles) while scattered threadgroup access patterns are the true bottleneck. Our multi-size implementation supports N!=!256 through N!=!16384 using a four-step decomposition for sizes exceeding the 32~KiB threadgroup memory limit. All kernels are validated against vDSP reference outputs.