# Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference

arXiv: https://arxiv.org/abs/2603.14091 · HTML: https://mlsanity.com/paper/2603.14091/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 11 of its 30 references that are in the map.
- First posted on arXiv 14 Mar 2026.

## Builds on (most cited first, 11 of 11)

- [FINN: A Framework for Fast, Scalable Binarized Neural Network Inference](https://mlsanity.com/paper/1612.07119/) (2016)
- [Satellite Communications in the New Space Era: A Survey and Future Challenges](https://mlsanity.com/paper/2002.08811/) (2020)
- [A Machine Learning Dataset Prepared From the NASA Solar Dynamics Observatory Mission](https://mlsanity.com/paper/1903.04538/) (2019)
- [Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA](https://mlsanity.com/paper/2301.01454/) (2023)
- [Automated classification of plasma regions using 3D particle energy distributions](https://mlsanity.com/paper/1908.05715/) (2019)
- [Efficient FPGA-accelerated Convolutional Neural Networks for Cloud Detection on CubeSats](https://mlsanity.com/paper/2504.03891/) (2025)
- [An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery](https://mlsanity.com/paper/2407.17647/) (2024)
- [Resource-constrained FPGA Design for Satellite Component Feature Extraction](https://mlsanity.com/paper/2301.09055/) (2023)
- [AI in Space for Scientific Missions: Strategies for Minimizing Neural-Network Model Upload](https://mlsanity.com/paper/2406.14297/) (2024)
- [FPGA-Based Neural Network Accelerators for Space Applications: A Survey](https://mlsanity.com/paper/2504.16173/) (2025)
- [Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications](https://mlsanity.com/paper/2506.12970/) (2025)

## Abstract (arXiv)

Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16× higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4× speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions.