# Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL

arXiv: https://arxiv.org/abs/2603.09161 · HTML: https://mlsanity.com/paper/2603.09161/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 13 of its 34 references that are in the map.
- First posted on arXiv 10 Mar 2026.

## Builds on (most cited first, 13 of 13)

- [Embodied LLM Agents Learn to Cooperate in Organized Teams](https://mlsanity.com/paper/2403.12482/) (2024)
- [RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution](https://mlsanity.com/paper/2312.08617/) (2023)
- [LLM Voting: Human Choices and AI Collective Decision Making](https://mlsanity.com/paper/2402.01766/) (2024)
- [Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework](https://mlsanity.com/paper/2403.11202/) (2024)
- [DeepGate2: Functionality-Aware Circuit Representation Learning](https://mlsanity.com/paper/2305.16373/) (2023)
- [DeepGate3: Towards Scalable Circuit Representation Learning](https://mlsanity.com/paper/2407.11095/) (2024)
- [HW2VEC: A Graph Learning Tool for Automating Hardware Security](https://mlsanity.com/paper/2107.12328/) (2021)
- [GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection](https://mlsanity.com/paper/2107.09130/) (2021)
- [CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design](https://mlsanity.com/paper/2505.02168/) (2025)
- [Hardware Trojan Detection using Graph Neural Networks](https://mlsanity.com/paper/2204.11431/) (2022)
- [AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networks](https://mlsanity.com/paper/2208.10868/) (2022)
- [Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism](https://mlsanity.com/paper/2505.21988/) (2025)
- [TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs](https://mlsanity.com/paper/2506.17894/) (2025)

## Abstract (arXiv)

Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate. Existing work therefore focuses on small-scale circuits with clean labels, limiting scalability to realistic designs. Meanwhile, Large Language Models (LLMs) can generate Register-Transfer-Level (RTL) at scale, but their functional incorrectness has hindered their use in circuit analysis. In this work, we make a key observation: even when LLM-Generated RTL is functionally imperfect, the synthesized netlists still preserve structural patterns that are strongly indicative of the intended functionality. Building on this insight, we propose a cost-effective data augmentation and training framework that systematically exploits imperfect LLM-Generated RTL as training data for netlist representation learning, forming an end-to-end pipeline from automated code generation to downstream tasks. We conduct evaluations on circuit functional understanding tasks, including sub-circuit boundary identification and component classification, across benchmarks of increasing scales, extending the task scope from operator-level to IP-level. The evaluations demonstrate that models trained on our noisy synthetic corpus generalize well to real-world netlists, matching or even surpassing methods trained on scarce high-quality data and effectively breaking the data bottleneck in circuit representation learning.