# Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review

arXiv: https://arxiv.org/abs/2603.08740 · HTML: https://mlsanity.com/paper/2603.08740/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 33 of its 148 references that are in the map.
- First posted on arXiv 25 Feb 2026.

## Builds on (most cited first, 30 of 33)

- [In-Datacenter Performance Analysis of a Tensor Processing Unit](https://mlsanity.com/paper/1704.04760/) (2017)
- [Speeding-up Convolutional Neural Networks Using Fine-tuned CP-Decomposition](https://mlsanity.com/paper/1412.6553/) (2014)
- [Bit-Flip Attack: Crushing Neural Network with Progressive Bit Search](https://mlsanity.com/paper/1903.12269/) (2019)
- [NVIDIA Tensor Core Programmability, Performance & Precision](https://mlsanity.com/paper/1803.04014/) (2018)
- [ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA](https://mlsanity.com/paper/1612.00694/) (2016)
- [FPGA-based Accelerators of Deep Learning Networks for Learning and Classification: A Review](https://mlsanity.com/paper/1901.00121/) (2019)
- [Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions](https://mlsanity.com/paper/1803.05900/) (2018)
- [EdgeDRNN: Recurrent Neural Network Accelerator for Edge Inference](https://mlsanity.com/paper/2012.13600/) (2020)
- [A Deep Attentive Convolutional Neural Network for Automatic Cortical Plate Segmentation in Fetal MRI](https://mlsanity.com/paper/2004.12847/) (2020)
- [An OpenCL(TM) Deep Learning Accelerator on Arria 10](https://mlsanity.com/paper/1701.03534/) (2017)
- [GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design](https://mlsanity.com/paper/2112.11594/) (2021)
- [FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks with Efficient DSP and Memory Optimization](https://mlsanity.com/paper/2301.01905/) (2023)
- [Randomized Tensor Ring Decomposition and Its Application to Large-scale Data Reconstruction](https://mlsanity.com/paper/1901.01652/) (2019)
- [BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices](https://mlsanity.com/paper/2104.06214/) (2021)
- [Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks](https://mlsanity.com/paper/2304.11761/) (2023)
- [Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference](https://mlsanity.com/paper/2307.09357/) (2023)
- [FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs](https://mlsanity.com/paper/1807.04093/) (2018)
- [Automatic Compiler Based FPGA Accelerator for CNN Training](https://mlsanity.com/paper/1908.06724/) (2019)
- [Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance](https://mlsanity.com/paper/2203.07516/) (2022)
- [DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs](https://mlsanity.com/paper/2305.05187/) (2023)
- [DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators](https://mlsanity.com/paper/2404.13049/) (2024)
- [Deep Convolutional Neural Networks Meet Variational Shape Compactness Priors for Image Segmentation](https://mlsanity.com/paper/2406.19400/) (2024)
- [FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration with Reconfigurable Spatial Architecture](https://mlsanity.com/paper/2408.15578/) (2024)
- [Dynasparse: Accelerating GNN Inference through Dynamic Sparsity Exploitation](https://mlsanity.com/paper/2303.12901/) (2023)
- [DASH: A Meta-Attack Framework for Synthesizing Effective and Stealthy Adversarial Examples](https://mlsanity.com/paper/2508.13309/) (2025)
- [CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Networks](https://mlsanity.com/paper/1703.07348/) (2017)
- [AccUDNN: A GPU Memory Efficient Accelerator for Training Ultra-deep Neural Networks](https://mlsanity.com/paper/1901.06773/) (2019)
- [Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design Methodology](https://mlsanity.com/paper/2410.16298/) (2024)
- [Runtime Detection of Adversarial Attacks in AI Accelerators Using Performance Counters](https://mlsanity.com/paper/2503.07568/) (2025)
- [Hardware Efficient Accelerator for Spiking Transformer With Reconfigurable Parallel Time Step Computing](https://mlsanity.com/paper/2503.19643/) (2025)

## Abstract (arXiv)

Deep learning (DL) has emerged as a rapidly developing advanced technology, enabling the performance of complex tasks involving image recognition, natural language processing, and autonomous decision-making with high levels of accuracy. However, as these technologies evolve and strive to meet the growing demands of real-life applications, the complexity of DL models continues to increase. These models require processing of massive volumes of data, demanding substantial computational power and memory bandwidth. This gives rise to the critical need for hardware accelerators that can deliver both high performance and energy efficiency. Accelerator types include ASIC based solutions, GPU accelerators, and FPGA based implementations. The limitations of ASIC and GPU accelerators have led to FPGAs becoming one of the prominent solutions, offering distinct advantages for DL workloads. FPGAs provide a flexible and reconfigurable platform, allowing model specific customization while maintaining high efficiency. This article explores various hardware level optimizations for DL. These optimizations include techniques such as loop pipelining, parallelism, quantization, and various memory hierarchy enhancements. In addition, it provides an overview of state-of-the-art FPGA-based neural network accelerators. Through the study and analysis of these accelerators, several challenges have been identified, paving the way for future optimizations and innovations in the design of FPGA-based hardware accelerators.