# Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU

arXiv: https://arxiv.org/abs/2603.08716 · HTML: https://mlsanity.com/paper/2603.08716/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Builds on 0 of its 4 references that are in the map.
- First posted on arXiv 6 Feb 2026.

## Built on by (most cited first, 4 of 4)

- [Computer Architecture's AlphaZero Moment: Automated Discovery in an Encircled World](https://mlsanity.com/paper/2604.03312/) (2026)
- [Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours](https://mlsanity.com/paper/2605.05170/) (2026)
- [CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents](https://mlsanity.com/paper/2607.16632/) (2026)
- [Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows](https://mlsanity.com/paper/2607.17528/) (2026)

## Abstract (arXiv)

Design Conductor (DC) is an autonomous agent which applies the capabilities of frontier models to build semiconductors end-to-end -- that is, from concept to verified, tape-out ready GDSII (layout CAD file). In 12 hours and fully autonomously, DC was able to build several micro-architecture variations of a complete RISC-V CPU (which we dub VerCore) that meet timing at 1.48 GHz (rv32i-zmmul; using the ASAP7 PDK), starting from a 219-word requirements document. The VerCore achieves a CoreMark score of 3261. For historical context, this is roughly equivalent to an Intel Celeron SU2300 from mid-2011 (which ran at 1.2 GHz). To our knowledge, this is the first time an autonomous agent has built a complete, working CPU from spec to GDSII. This report is organized as follows. We first review DC's design and its key components. We then describe the methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools. We review the key characteristics of the resulting VerCore. Finally, we highlight how frontier models could improve to better enable this application, and our lessons learned as to how chips will be built in the future enabled by the capabilities of systems like DC.