# When Small Variations Become Big Failures: Reliability Challenges in Compute-in-Memory Neural Accelerators

arXiv: https://arxiv.org/abs/2603.03491 · HTML: https://mlsanity.com/paper/2603.03491/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 7 references that are in the map.
- First posted on arXiv 3 Mar 2026.

## Builds on (most cited first, 5 of 5)

- [SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators](https://mlsanity.com/paper/2202.08395/) (2022)
- [Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?](https://mlsanity.com/paper/2207.07626/) (2022)
- [Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise](https://mlsanity.com/paper/2307.15853/) (2023)
- [TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators](https://mlsanity.com/paper/2406.06544/) (2024)
- [NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Accelerators](https://mlsanity.com/paper/2305.14561/) (2023)

## Built on by (most cited first, 1 of 1)

- [Interface-Aware KV Cache Quantization for Dense On-Chip NVM in Long-Context LLM Decoding](https://mlsanity.com/paper/2609.05764/) (2026)

## Abstract (arXiv)

Compute-in-memory (CiM) architectures promise significant improvements in energy efficiency and throughput for deep neural network acceleration by alleviating the von Neumann bottleneck. However, their reliance on emerging non-volatile memory devices introduces device-level non-idealities-such as write variability, conductance drift, and stochastic noise-that fundamentally challenge reliability, predictability, and safety, especially in safety-critical applications. This talk examines the reliability limits of CiM-based neural accelerators and presents a series of techniques that bridge device physics, architecture, and learning algorithms to address these challenges. We first demonstrate that even small device variations can lead to disproportionately large accuracy degradation and catastrophic failures in safety-critical inference workloads, revealing a critical gap between average-case evaluations and worst-case behavior. Building on this insight, we introduce SWIM, a selective write-verify mechanism that strategically applies verification only where it is most impactful, significantly improving reliability while maintaining CiM's efficiency advantages. Finally, we explore a learning-centric solution that improves realistic worst-case performance by training neural networks with right-censored Gaussian noise, aligning training assumptions with hardware-induced variability and enabling robust deployment without excessive hardware overhead. Together, these works highlight the necessity of cross-layer co-design for CiM accelerators and provide a principled path toward dependable, efficient neural inference on emerging memory technologies-paving the way for their adoption in safety- and reliability-critical systems.