# TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference

arXiv: https://arxiv.org/abs/2603.03075 · HTML: https://mlsanity.com/paper/2603.03075/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 1 of its 16 references that are in the map.
- First posted on arXiv 3 Mar 2026.

## Builds on (most cited first, 1 of 1)

- [Enhancing sea ice segmentation in Sentinel-1 images with atrous convolutions](https://mlsanity.com/paper/2310.17122/) (2023)

## Abstract (arXiv)

Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.