# ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification

arXiv: https://arxiv.org/abs/2603.01170 · HTML: https://mlsanity.com/paper/2603.01170/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 7 of its 56 references that are in the map.
- First posted on arXiv 1 Mar 2026.

## Builds on (most cited first, 7 of 7)

- [Spectre Attacks: Exploiting Speculative Execution](https://mlsanity.com/paper/1801.01203/) (2018)
- [Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation](https://mlsanity.com/paper/2407.08473/) (2024)
- [SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation](https://mlsanity.com/paper/2508.03558/) (2025)
- [VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation](https://mlsanity.com/paper/2507.13369/) (2025)
- [ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification](https://mlsanity.com/paper/2505.06821/) (2025)
- [MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors](https://mlsanity.com/paper/2311.14594/) (2023)
- [Security Properties for Open-Source Hardware Designs](https://mlsanity.com/paper/2412.08769/) (2024)

## Abstract (arXiv)

This work presents ATLAS, an LLM-driven framework that bridges standardized threat modeling and property-based formal verification for System-on-Chip (SoC) security. Starting from vulnerability knowledge bases such as Common Weakness Enumeration (CWE), ATLAS identifies SoC-specific assets, maps relevant weaknesses, and generates assertion-based security properties and JasperGold scripts for verification. By combining asset-centric analysis with standardized threat model templates and multi-source SoC context, ATLAS automates the transformation from vulnerability reasoning to formal proof. Evaluated on three HACK@DAC benchmarks, ATLAS detected 39/48 CWEs and generated correct properties for 33 of those bugs, advancing automated, knowledge-driven SoC security verification toward a secure-by-design paradigm.