# DARTH-PUM: A Hybrid Processing-Using-Memory Architecture

arXiv: https://arxiv.org/abs/2602.16075 · HTML: https://mlsanity.com/paper/2602.16075/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 29 of its 165 references that are in the map.
- First posted on arXiv 17 Feb 2026.

## Builds on (most cited first, 29 of 29)

- [Deep Residual Learning for Image Recognition](https://mlsanity.com/paper/1512.03385/) (2015)
- [BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding](https://mlsanity.com/paper/1810.04805/) (2018)
- [PyTorch: An Imperative Style, High-Performance Deep Learning Library](https://mlsanity.com/paper/1912.01703/) (2019)
- [LLaMA: Open and Efficient Foundation Language Models](https://mlsanity.com/paper/2302.13971/) (2023)
- [I-BERT: Integer-only BERT Quantization](https://mlsanity.com/paper/2101.01321/) (2021)
- [PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference](https://mlsanity.com/paper/1901.10351/) (2019)
- [RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing](https://mlsanity.com/paper/1912.12953/) (2019)
- [Exploring Transformers in Natural Language Generation: GPT, BERT, and XLNet](https://mlsanity.com/paper/2102.08036/) (2021)
- [GraphR: Accelerating Graph Processing Using ReRAM](https://mlsanity.com/paper/1708.06248/) (2017)
- [Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator](https://mlsanity.com/paper/1707.09952/) (2017)
- [FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator](https://mlsanity.com/paper/2106.09144/) (2021)
- [Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation](https://mlsanity.com/paper/2209.00606/) (2022)
- [DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks](https://mlsanity.com/paper/2105.03725/) (2021)
- [RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!](https://mlsanity.com/paper/2304.07935/) (2023)
- [QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips](https://mlsanity.com/paper/2105.08955/) (2021)
- [Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration](https://mlsanity.com/paper/1803.06913/) (2018)
- [PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System](https://mlsanity.com/paper/2404.07164/) (2024)
- [FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture](https://mlsanity.com/paper/1901.09904/) (2019)
- [PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM](https://mlsanity.com/paper/2111.00082/) (2021)
- [DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips](https://mlsanity.com/paper/2211.05838/) (2022)
- [Hybrid SLC-MLC RRAM Mixed-Signal Processing-in-Memory Architecture for Transformer Acceleration via Gradient Redistribution](https://mlsanity.com/paper/2506.00020/) (2025)
- [ReFloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers](https://mlsanity.com/paper/2011.03190/) (2020)
- [Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis](https://mlsanity.com/paper/2402.18736/) (2024)
- [Device-aware inference operations in SONOS nonvolatile memory arrays](https://mlsanity.com/paper/2004.00802/) (2020)
- [OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration](https://mlsanity.com/paper/2308.15040/) (2023)
- [HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads](https://mlsanity.com/paper/2403.13577/) (2024)
- [Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis](https://mlsanity.com/paper/2405.06081/) (2024)
- [Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing](https://mlsanity.com/paper/2501.09902/) (2025)
- [Analog fast Fourier transforms for scalable and efficient signal processing](https://mlsanity.com/paper/2409.19071/) (2024)

## Abstract (arXiv)

Analog processing-using-memory (PUM; a.k.a. in-memory computing) makes use of electrical interactions inside memory arrays to perform bulk matrix-vector multiplication (MVM) operations. However, many popular matrix-based kernels need to execute non-MVM operations, which analog PUM cannot directly perform. To retain its energy efficiency, analog PUM architectures augment memory arrays with CMOS-based domain-specific fixed-function hardware to provide complete kernel functionality, but the difficulty of integrating such specialized CMOS logic with memory arrays has largely limited analog PUM to being an accelerator for machine learning inference, or for closely related kernels. An opportunity exists to harness analog PUM for general-purpose computation: recent works have shown that memory arrays can also perform Boolean PUM operations, albeit with very different supporting hardware and electrical signals than analog PUM. We propose DARTH-PUM, a general-purpose hybrid PUM architecture that tackles key hardware and software challenges to integrating analog PUM and digital PUM. We propose optimized peripheral circuitry, coordinating hardware to manage and interface between both types of PUM, an easy-to-use programming interface, and low-cost support for flexible data widths. These design elements allow us to build a practical PUM architecture that can execute kernels fully in memory, and can scale easily to cater to domains ranging from embedded applications to large-scale data-driven computing. We show how three popular applications (AES encryption, convolutional neural networks, large language models) can map to and benefit from DARTH-PUM, with speedups of 59.4x, 14.8x, and 40.8x over an analog+CPU baseline.