# DRAMPyML: A Formal Description of DRAM Protocols with Timed Petri Nets

arXiv: https://arxiv.org/abs/2602.10654 · HTML: https://mlsanity.com/paper/2602.10654/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 11 Feb 2026.

## Built on by (most cited first, 1 of 1)

- [Autoformalizing Memory Specifications with Agents](https://mlsanity.com/paper/2605.00058/) (2026)

## Abstract (arXiv)

The JEDEC committee defines various domain-specific DRAM standards. These standards feature increasingly complex and evolving protocol specifications, which are detailed in timing diagrams and command tables. Understanding these protocols is becoming progressively challenging as new features and complex device hierarchies are difficult to comprehend without an expressive model. While each JEDEC standard features a simplified state machine, this state machine fails to reflect the parallel operation of memory banks. In this paper, we present an evolved modeling approach based on timed Petri nets and Python. This model provides a more accurate representation of DRAM protocols, making them easier to understand and directly executable, which enables the evaluation of interesting metrics and the verification of controller RTL models, DRAM logic and memory simulators.