# Analysis of Edge Mismatch and Output Power Degradation in Cascoded Class-D Power Amplifiers Using Dual-Range Voltage Level Shifters

arXiv: https://arxiv.org/abs/2602.09820 · HTML: https://mlsanity.com/paper/2602.09820/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 10 Feb 2026.

## Built on by (most cited first, 1 of 1)

- [Enabling Spatially Fine-Grained DVFS in Neural Processing Units for Energy-Efficient LLM Serving](https://mlsanity.com/paper/2607.16473/) (2026)

## Abstract (arXiv)

This paper presents a low-jitter acHVLS architecture for high-speed mixed-signal and digital power-amplifier applications. The proposed design employs a regenerative cross-coupled feedback network to simultaneously generate two synchronized voltage-domain outputs (e.g., the nominal supply voltage (VDDL) and one at twice its value (VDDH = 2VDDL)). This enables direct drive of cascoded class-D power amplifiers without additional delay-calibration circuitry, amongst other mixed-signal applications. A prototype acHVLS circuit, together with an impedance-matching network and a pre-driver for high-speed off-chip characterization, was fabricated in a 22-nm FD-SOI process technology. The total die area, including all interface circuitry, is 477×462~μm2, while the active area of the acHVLS core is 3.26×2~μm2. Measured at 12.2~GHz, the circuit dissipates 4.43~μW per switching cycle and achieves an output jitter below 150~fs-rms.