# SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence

arXiv: https://arxiv.org/abs/2601.22114 · HTML: https://mlsanity.com/paper/2601.22114/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Builds on 7 of its 16 references that are in the map.
- First posted on arXiv 29 Jan 2026.

## Builds on (most cited first, 7 of 7)

- [GPT-4 Technical Report](https://mlsanity.com/paper/2303.08774/) (2023)
- [You Only Look Once: Unified, Real-Time Object Detection](https://mlsanity.com/paper/1506.02640/) (2015)
- [VeriGen: A Large Language Model for Verilog Code Generation](https://mlsanity.com/paper/2308.00708/) (2023)
- [Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI](https://mlsanity.com/paper/2411.14299/) (2024)
- [Schemato -- An LLM for Netlist-to-Schematic Conversion](https://mlsanity.com/paper/2411.13899/) (2024)
- [MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation](https://mlsanity.com/paper/2508.08137/) (2025)
- [Tablext: A Combined Neural Network And Heuristic Based Table Extractor](https://mlsanity.com/paper/2104.11287/) (2021)

## Built on by (most cited first, 4 of 4)

- [OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoning](https://mlsanity.com/paper/2604.00270/) (2026)
- [ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration](https://mlsanity.com/paper/2608.04999/) (2026)
- [SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence](https://mlsanity.com/paper/2607.01609/) (2026)
- [AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models](https://mlsanity.com/paper/2608.13472/) (2026)

## Abstract (arXiv)

Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.