# SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency

arXiv: https://arxiv.org/abs/2601.17279 · HTML: https://mlsanity.com/paper/2601.17279/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 8 of its 18 references that are in the map.
- First posted on arXiv 24 Jan 2026.

## Builds on (most cited first, 8 of 8)

- [Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads](https://mlsanity.com/paper/2412.11702/) (2024)
- [Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In](https://mlsanity.com/paper/2305.04760/) (2023)
- [Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing](https://mlsanity.com/paper/2503.04581/) (2025)
- [HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator](https://mlsanity.com/paper/2409.04976/) (2024)
- [Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET](https://mlsanity.com/paper/2501.07330/) (2025)
- [XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads](https://mlsanity.com/paper/2508.13049/) (2025)
- [PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications](https://mlsanity.com/paper/2302.01876/) (2023)
- [RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN](https://mlsanity.com/paper/2510.22627/) (2025)

## Built on by (most cited first, 1 of 1)

- [SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC](https://mlsanity.com/paper/2606.09946/) (2026)

## Abstract (arXiv)

The growing demand for edge-AI systems requires arithmetic units that balance numerical precision, energy efficiency, and compact hardware while supporting diverse formats. Posit arithmetic offers advantages over floating- and fixed-point representations through its tapered precision, wide dynamic range, and improved numerical robustness. This work presents SPADE, a unified multi-precision SIMD Posit-based multiplyaccumulate (MAC) architecture supporting Posit (8,0), Posit (16,1), and Posit (32,2) within a single framework. Unlike prior single-precision or floating/fixed-point SIMD MACs, SPADE introduces a regime-aware, lane-fused SIMD Posit datapath that hierarchically reuses Posit-specific submodules (LOD, complementor, shifter, and multiplier) across 8/16/32-bit precisions without datapath replication. FPGA implementation on a Xilinx Virtex-7 shows 45.13% LUT and 80% slice reduction for Posit (8,0), and up to 28.44% and 17.47% improvement for Posit (16,1) and Posit (32,2) over prior work, with only 6.9% LUT and 14.9% register overhead for multi-precision support. ASIC results across TSMC nodes achieve 1.38 GHz at 6.1 mW (28 nm). Evaluation on MNIST, CIFAR-10/100, and alphabet datasets confirms competitive inference accuracy.